A Suggestion for a fast residue multiplier for a family of moduli of the form (2n-(2p±1))

被引:16
作者
Hiasat, AA [1 ]
机构
[1] Princess Sumaya Univ, Dept Elect Engn, Amman 11941, Jordan
关键词
D O I
10.1093/comjnl/47.1.93
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
The family of moduli that has the form (2(n) - (2(p) +/- 1)) is considered in this paper. A suggestion for a fast residue multiplier for this family of moduli is introduced. The multiplication algorithm proposed in this paper generates (2n + p - 2) partial products; however, it compresses the magnitude of each partial product to be less than 2(n). Although it requires an additional integrated circuit area compared with the most recent published study, the new proposed modular multiplier has a logarithmic delay, which makes it faster than any other modular multiplier. Moreover, it is even faster than binary-based iterative array multipliers with a final CLA addition. The proposed modular multiplier is very suitable for medium and large dynamic ranges.
引用
收藏
页码:93 / 102
页数:10
相关论文
共 32 条
[1]   A VLSI MODULO-M MULTIPLIER [J].
ALIA, G ;
MARTINELLI, E .
IEEE TRANSACTIONS ON COMPUTERS, 1991, 40 (07) :873-878
[2]   An RNS Montgomery modular multiplication algorithm [J].
Bajard, JC ;
Didier, LS ;
Kornerup, P .
IEEE TRANSACTIONS ON COMPUTERS, 1998, 47 (07) :766-776
[3]   Delta-Sigma modulator with large OSR using the One-Hot Residue Number System [J].
Chren, WA .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING, 1999, 46 (08) :1002-1008
[4]   REGULAR VLSI ARCHITECTURES FOR MULTIPLICATION MODULO (2N + 1) [J].
CURIGER, AV ;
BONNENBERG, H ;
KAESLIN, H .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1991, 26 (07) :990-994
[5]   FAST COMBINATORIAL RNS PROCESSORS FOR DSP APPLICATIONS [J].
DICLAUDIO, ED ;
PIAZZA, F ;
ORLANDI, G .
IEEE TRANSACTIONS ON COMPUTERS, 1995, 44 (05) :624-633
[6]   RESIDUE MULTIPLIERS USING FACTORED DECOMPOSITION [J].
DUGDALE, M .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING, 1994, 41 (09) :623-627
[7]   A SYSTOLIC ARCHITECTURE FOR MODULE MULTIPLICATION [J].
ELLEITHY, KM ;
BAYOUMI, MA .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING, 1995, 42 (11) :725-729
[8]  
HIASAT A, 1991, ELECTRON LETT, V28, P414
[9]   Efficient residue to binary converter [J].
Hiasat, AA .
IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES, 2003, 150 (01) :11-16
[10]   High-speed and reduced-area modular adder structures for RNS [J].
Hiasat, AA .
IEEE TRANSACTIONS ON COMPUTERS, 2002, 51 (01) :84-89