A unified architecture for adaptive compression of data and code on embedded systems

被引:9
作者
Lekatsas, H
Henkel, J
Jakkula, V
Chakradhar, S
机构
来源
18TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS: POWER AWARE DESIGN OF VLSI SYSTEMS | 2005年
关键词
D O I
10.1109/ICVD.2005.36
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
We present an architecture for compression/decompression of executable files running on embedded systems. Compression is important for memory reduction purposes; previous work on memory reduction for embedded systems has focused on compressing the instruction segment of executable code before execution and decompressing at runtime. Our work has shown that solely compressing the instruction segment is not enough as in many cases executable files contain large data areas that would benefit from compression as well. Compressing data areas presents new challenges to the embedded system designer, data can be modified during execution and therefore a fast compression algorithm and intelligent memory management are required as well. We propose a novel compression/decompression framework that can handle both instructions and data and show memory reductions over 50% while keeping performance degradation within 12%.
引用
收藏
页码:117 / 123
页数:7
相关论文
共 7 条
  • [1] [Anonymous], 1990, Text Compression
  • [2] BENINI L, HARDWARE ASSISTED DA
  • [3] KJELSO M, 1996, 22 EUR C SEPT, P423
  • [4] PECK JEL, 1975, TR7502 DEP COMP SCI
  • [5] SHAW C, 2003, 16 INT C VLSI DES JA
  • [6] TREMAINE B, 2001, IBM J RES DEV, V45
  • [7] 5761536