The mathematics of a quantum Hamiltonian computing half adder Boolean logic gate

被引:12
|
作者
Dridi, G. [1 ,2 ]
Julien, R. [1 ,2 ,3 ]
Hliwa, M. [1 ,2 ,4 ]
Joachim, C. [1 ,2 ,5 ]
机构
[1] CEMES CNRS, Nanosci Grp, F-31055 Toulouse, France
[2] CEMES CNRS, MANA Satellite, F-31055 Toulouse, France
[3] ISAE SUPAERO, Toulouse, France
[4] Univ Hassan II Casablanca, Fac Sci Ben MSik, Casablanca, Morocco
[5] Natl Inst Mat Sci NIMS, Int Ctr Mat Nanoarchitechton MANA, Tsukuba, Ibaraki 3050044, Japan
关键词
quantum state; quantum computing; logic gates; nanoscale;
D O I
10.1088/0957-4484/26/34/344003
中图分类号
TB3 [工程材料学];
学科分类号
0805 ; 080502 ;
摘要
The mathematics behind the quantum Hamiltonian computing (QHC) approach of designing Boolean logic gates with a quantum system are given. Using the quantum eigenvalue repulsion effect, the QHC AND, NAND, OR, NOR, XOR, and NXOR Hamiltonian Boolean matrices are constructed. This is applied to the construction of a QHC half adder Hamiltonian matrix requiring only six quantum states to fullfil a half Boolean logical truth table. The QHC design rules open a nano-architectronic way of constructing Boolean logic gates inside a single molecule or atom by atom at the surface of a passivated semi-conductor.
引用
收藏
页数:8
相关论文
共 50 条
  • [31] Timing-Aware Qubit Mapping and Gate Scheduling Adapted to Neutral Atom Quantum Computing
    Li, Yongshang
    Zhang, Yu
    Chen, Mingyu
    Li, Xiangyang
    Xu, Peng
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2023, 42 (11) : 3768 - 3780
  • [32] Majority-Logic-Based Self-Checking Adder in Quantum-Dot Cellular Automata
    Raj, Marshal
    Sekar, K. Raja
    Lakshminarayanan, G.
    IEEE DESIGN & TEST, 2022, 39 (05) : 88 - 97
  • [33] Quantum reinforcement learningComparing quantum annealing and gate-based quantum computing with classical deep reinforcement learning
    Niels M. P. Neumann
    Paolo B. U. L. de Heer
    Frank Phillipson
    Quantum Information Processing, 22
  • [34] A Direct Inverter Gate Logic Circuit Based on Quantum Phase Slip Junctions
    Malekpoor, Azam
    Hashemi, Seyed Amir
    Jit, Satyabrata
    IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, 2022, 32 (08)
  • [35] Nuclear spin based memory and logic in quantum Hall semiconductor nanostructures for quantum computing applications
    Mani, RG
    Johnson, WB
    Narayanamurti, V
    Privman, V
    Zhang, YH
    PHYSICA E-LOW-DIMENSIONAL SYSTEMS & NANOSTRUCTURES, 2002, 12 (1-4) : 152 - 156
  • [36] 50-GFLOPS Floating-Point Adder and Multiplier Using Gate-Level-Pipelined Single-Flux-Quantum Logic With Frequency-Increased Clock Distribution
    Nagaoka, Ikki
    Kashima, Ryota
    Tanaka, Masamitsu
    Kawakami, Satoshi
    Tanimoto, Teruo
    Yamashita, Taro
    Inoue, Koji
    Fujimaki, Akira
    IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, 2023, 33 (04)
  • [37] Quantum reinforcement learning Comparing quantum annealing and gate-based quantum computing with classical deep reinforcement learning
    Neumann, Niels M. P.
    de Heer, Paolo B. U. L.
    Phillipson, Frank
    QUANTUM INFORMATION PROCESSING, 2023, 22 (02)
  • [38] In-Depth Timing Characterization of the Adiabatic Quantum-Flux-Parametron Logic Gate
    Hoshika, Yu
    Ayala, Christopher L.
    Yoshikawa, Nobuyuki
    IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, 2024, 34 (04) : 1 - 8
  • [39] Transmission Line Effects of Long Gate-to-Gate Interconnections in Adiabatic Quantum-Flux-Parametron Logic Circuits
    Asai, Kazuhito
    Takeuchi, Naoki
    Suzuki, Hideo
    Yamanashi, Yuki
    Yoshikawa, Nobuyuki
    IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, 2022, 32 (07)
  • [40] Logic Computing Field-Effect Transistors Based on a Monolayer WSe2 Homojunction for the Semi-adder and Decoder
    Li, Xueping
    Wang, Zhuojun
    Tang, Xiaojie
    Yuan, Peize
    Li, Lin
    Shen, Chenhai
    Jiang, Yurong
    Song, Xiaohui
    Xia, Congxin
    NANO LETTERS, 2024, 24 (35) : 11132 - 11139