Cache RAM inductive fault analysis with Fab defect modeling
被引:14
作者:
Mak, TM
论文数: 0引用数: 0
h-index: 0
机构:
Intel Corp, Santa Clara, CA 95052 USAIntel Corp, Santa Clara, CA 95052 USA
Mak, TM
[1
]
Bhattacharya, D
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h-index: 0
机构:
Intel Corp, Santa Clara, CA 95052 USAIntel Corp, Santa Clara, CA 95052 USA
Bhattacharya, D
[1
]
Prunty, C
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h-index: 0
机构:
Intel Corp, Santa Clara, CA 95052 USAIntel Corp, Santa Clara, CA 95052 USA
Prunty, C
[1
]
Roeder, B
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h-index: 0
机构:
Intel Corp, Santa Clara, CA 95052 USAIntel Corp, Santa Clara, CA 95052 USA
Roeder, B
[1
]
Ramadan, N
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机构:
Intel Corp, Santa Clara, CA 95052 USAIntel Corp, Santa Clara, CA 95052 USA
Ramadan, N
[1
]
Ferguson, J
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机构:
Intel Corp, Santa Clara, CA 95052 USAIntel Corp, Santa Clara, CA 95052 USA
Ferguson, J
[1
]
Yu, JL
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h-index: 0
机构:
Intel Corp, Santa Clara, CA 95052 USAIntel Corp, Santa Clara, CA 95052 USA
Yu, JL
[1
]
机构:
[1] Intel Corp, Santa Clara, CA 95052 USA
来源:
INTERNATIONAL TEST CONFERENCE 1998, PROCEEDINGS
|
1998年
关键词:
D O I:
10.1109/TEST.1998.743275
中图分类号:
TP3 [计算技术、计算机技术];
学科分类号:
0812 ;
摘要:
This paper describes how an Inductive Fault Analysis (IFA) method was used in determining the expected yield and test algorithm effectiveness in SRAMs. One portion of the paper describes the process of gathering and correlating defect data from different sources to get a meaningful and accurate defect distribution. This data is used in the IFA software to weight the probability of faults occurring. With the fault data from two SRAM cells the yield of those devices is estimated and compared with actual yield. The effectiveness of certain test patterns is also evaluated based on the probable faults for those circuits.