25-Gbps 5 x 5 mm2 Chip-Scale Silicon-Photonic Receiver Integrated with 28-nm CMOS Transimpedance Amplifier

被引：0

作者：

Okamoto, Daisuke ^{[1
]}

Suzuki, Yasuyuki ^{[1
]}

Yashiki, Kenichiro ^{[1
]}

Hagihara, Yasuhiko ^{[1
]}

Tokushima, Masatoshi ^{[1
]}

Fujikata, Junichi ^{[1
]}

Kurihara, Mitsuru ^{[1
]}

Tsuchida, Junichi ^{[1
]}

Nedachi, Takaaki ^{[1
]}

Inasaka, Jun ^{[1
]}

Kurata, Kazuhiko ^{[1
]}

机构：

[1] PETRA, West7A4F,16-1 Onogawa, Tsukuba, Ibaraki 3058569, Japan

来源：

2015 IEEE OPTICAL INTERCONNECTS CONFERENCE | 2015年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We have developed a compact silicon-photonic receiver integrated with a CMOS transimpedance amplifier (TIA) chip and demonstrated 25-Gbps error -free operation. A minimum sensitivity of 9.7 dBm and a consumption power of 2,3 mW/Gbps were obtained.

引用

页码：56 / 57

页数：2

共 2 条

[1] A 25-Gb/s 5 x 5 mm2 Chip-Scale Silicon-Photonic Receiver Integrated With 28-nm CMOS Transimpedance Amplifier
Okamoto, Daisuke
Suzuki, Yasuyuki
Yashiki, Kenichiro
Hagihara, Yasuhiko
Tokushima, Masatoshi
Fujikata, Junichi
Kurihara, Mitsuru
Tsuchida, Junichi
Nedachi, Takaaki
Inasaka, Jun
Kurata, Kazuhiko
JOURNAL OF LIGHTWAVE TECHNOLOGY, 2016, 34 (12) : 2988 - 2995
[2] A 0.05-mm2 2.91-nJ/Decision Keyword-Spotting (KWS) Chip Featuring an Always-Retention 5T-SRAM in 28-nm CMOS
Tan, Fei
Yu, Wei-Han
Un, Ka-Fai
Martins, Rui P. P.
Mak, Pui-In
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2024, 59 (02) : 626 - 635

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