Design optimization for capacitive-resistively driven on-chip global interconnect

被引：3
|
作者：
Jiang, Jianfei [1 ]
He, Weifeng [1 ]
Wei, Jizeng [2 ]
Wang, Qin [1 ]
Mao, Zhigang [1 ]
机构：
[1] Shanghai Jiao Tong Univ, Shanghai 200240, Peoples R China
[2] Tianjin Univ, Tianjin 300072, Peoples R China
来源：
IEICE ELECTRONICS EXPRESS | 2015年 / 12卷 / 08期
基金：
国家高技术研究发展计划(863计划); 中国国家自然科学基金;
关键词：
AC coupling; global interconnect; high speed; on-chip; low power; COMMUNICATION; TRANSCEIVER; SPEED; WIRES; CMOS;
D O I：
10.1587/elex.12.20150111
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
On-chip global wires are speed and power bottleneck in state-of-the-art chips. AC coupling technique is an efficient way to reduce interconnection delay and power. This paper proposes a new capacitive-resistively driven AC coupling global link. Bandwidth performance of the proposed wire is analyzed and an optimization algorithm for capacitive-resistively driven wire is presented. Simulation results show that our optimization methodology can improve the bandwidth. By applying our optimization algorithm, data rate can be improved from 2 Gb/s to 2.5 Gb/s in the implemented transceiver circuit. The proposed optimization algorithm can be applied in high speed global communication.
引用
收藏
页码：1 / 12
页数：12
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