Topology adaptive network-on-chip design and implementation

被引:29
作者
Bartic, TA
Mignolet, JY
Nollet, V
Marescaux, T
Verkest, D
Vernalde, S
Lauwereins, R
机构
[1] IMEC, B-3001 Louvain, Belgium
[2] Katholieke Univ Leuven, Louvain, Belgium
[3] Vrije Univ Brussels, Brussels, Belgium
来源
IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES | 2005年 / 152卷 / 04期
关键词
D O I
10.1049/ip-cdt:20045016
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Network-on-chip designs promise to offer considerable advantages over the traditional bus-based designs in solving the numerous technological, economic and productivity problems associated with billion-transistor system-on-chip development. The authors believe that different types of networks will be required, depending on the application domain. Therefore, a very flexible network design is proposed that is highly scalable, and can be easily changed to accomodate various needs. A network-on-chip design, realised as part of the platform that the authors are developing for reconfigurable systems, is presented. This design is suitable for building networks with irregular topologies, and with low latency and high throughput.
引用
收藏
页码:467 / 472
页数:6
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