A Fully Serial-In Parallel-Out Digit-Level Finite Field Multiplier in F2m Using Redundant Representation

Redundant basis (RB) is one of the appealing representation systems for finite field arithmetic due to its specific features in providing cost-free squaring operation in hardware implementation and because it eliminates the need for modular reduction. In this brief, a new architecture for digit-level finite field multiplication in F-2m using redundant representation is proposed. Contrary to previously presented redundant basis multipliers, in the proposed architecture one digit of each operand is concurrently fed into the multiplier at each clock cycle which, in turn, reduces the total number of the clock cycles required in the multiplication process. To draw an accurate comparison, the proposed multiplier together with several existing digit-level RB multipliers were fully implemented in 65-nm CMOS technology.