Different proposals to matrix multiplication based on FPGAs

Matrix multiplication is a typical operation in different engineering areas, such as signal or image processing. This paper makes a brief description about some matrix multiplication proposals when working in FPGAs (Field Programmable Gate Array). Thanks to their low prices and low costs, currently these devices are used in many and different applications. There are some alternative methods that optimize execution time to carry out this operation under FPGAs. The internal structure of these devices allows parallel execution of matrix multiplication. However, a systolic structure needs many internal resources such as embedded multipliers and often it cannot be used because of the low number of embedded multipliers in the used device. This structure is commonly used in FPGAs for small size matrices. However our proposed alternatives allow an efficient multiplication of matrices of sizes as big as 512 x 512 elements. The study done in this work compares the delay and area consumed of different matrix multiplication algorithms.