A High-Speed Low-Power Multitask Digital Vision Chip

被引：0

作者：

Noohi, Mohammad Sajad ^{[1
]}

Sayedi, Sayed Masoud ^{[1
]}

Jalili, Armin ^{[1
]}

机构：

[1] Isfahan Univ Technol, Dept Elect & Comp Engn, Esfahan, Iran

来源：

2014 SECOND RSI/ISM INTERNATIONAL CONFERENCE ON ROBOTICS AND MECHATRONICS (ICROM) | 2014年

关键词：

digital vision chip; in-pixel image processing; high speed general purpose vision chip; robotic vision; PROCESSOR; PIXEL;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A new pixel architecture for the use in a multitask digital vision chip is presented. The architecture is based on SIMD parallel processing, and it is configurable to perform different binary image processing operations in high speed and with low power consumption. The proposed circuit can output the result in each period of its operating frequency, which makes it very suitable for high speed real time applications. An array of 32*64 pixels has been simulated in 0.18 mu m CMOS technology. The array works at 80 MHz clock frequency, and each pixel of it only consumes 3.4 mu W. The results of image processing on the array show the high performance of the circuit.

引用

页码：161 / 165

页数：5

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