Area and Power Analysis of AES using Hardware and Software Co-Design

被引：0

作者：

Deotare, Vilas V. ^{[1
]}

Padole, Dinesh V. ^{[1
]}

Wakode, Ashok S. ^{[1
]}

机构：

[1] GHRCE Nagpur, Nagpur, Maharashtra, India

来源：

2014 IEEE GLOBAL CONFERENCE ON WIRELESS COMPUTING AND NETWORKING (GCWCN) | 2014年

关键词：

Time evaluation; Substitution; Encryption; Decryption Plain text; cipher text; key operating frequency; FPGA;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper investigate the analysis of power and area of Advanced Encryption Standard (AES) algorithm using different design tool like ARM based, Hardware (VHDL/Verilog) and HW/SW. Results of area and power consumption for different design are varying and the percentage improvement in the power and area is marginable. The power improvement range is between 22.5% to 90% and the area improvement range is between 5% to 30%. The proposed AES is implemented on different hardware like ARM, microblaze processor and FPGA.

引用

页码：194 / 198

页数：5

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