Design of hardware accelerator for Lempel-Ziv 4 (LZ4) compression

被引：12
|
作者：
Lee, Sang Muk [1 ]
Jang, Ji Hoon [1 ]
Oh, Jung Hwan [1 ]
Kim, Ji Kwang [1 ]
Lee, Seung Eun [1 ]
机构：
[1] Seoul Natl Univ Sci & Technol, Dept Elect Engn, 232 Gongreung Ro, Seoul 139743, South Korea
来源：
IEICE ELECTRONICS EXPRESS | 2017年 / 14卷 / 11期
关键词：
data compression; LZ4; hardware accelerator; high throughput;
D O I：
10.1587/elex.14.20170399
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Hardware accelerators are being considered as important architectural components in the context of datacenter customization to achieve high performance and low power. Compression has played an important role in computer systems by enhancing storage and communication efficiency in the charge of extra computational cost. In this letter, we present a fully pipelined compression accelerator for the Lempel-Ziv (LZ) compression algorithm. The compression accelerator is verified by using FPGA and fabricated using 65 nm CMOS technology.
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页数：6
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