Slew-aware Fast Clock Tree Synthesis with Buffer Sizing

被引:0
|
作者
Choi, Mujun [1 ]
Oh, Deokkeun [1 ]
Kim, Juho [1 ]
机构
[1] Sogang Univ, Dept Comp Sci & Engn, Seoul, South Korea
来源
2018 INTERNATIONAL CONFERENCE ON ELECTRONICS, INFORMATION, AND COMMUNICATION (ICEIC) | 2018年
关键词
skew; slew; buffer sizing; DME; Fast CTS;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Clock tree synthesis (CTS) is a critical part on the total performance of chip. Buffer insertion is required in clock tree to prevent signal degradation and satisfy slew constraints. Also, buffer sizing minimizes power and skew in clock tree network. In this paper, we proposed slew-aware fast buffer insertion/sizing methodology in CTS based on DME to meet the skew constraints. The experiment results show the proposed sizing method reduce about 13.47% power consumption and 49.03% runtime compared to LP-based method.
引用
收藏
页码:271 / 274
页数:4
相关论文
共 50 条
  • [31] Variation-aware clock network buffer sizing using robust multi-objective optimization
    Farshidi, Amin
    Rakai, Logan
    Behjat, Laleh
    Westwick, David
    OPTIMIZATION AND ENGINEERING, 2016, 17 (02) : 473 - 500
  • [32] Clock buffer and wire sizing using sequential programming
    Guthaus, Matthew R.
    Sylvester, Dennis
    Brown, Richard B.
    43RD DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 2006, 2006, : 1041 - +
  • [33] On-Chip-Variation-Aware Power-Mode-Aware Buffer Synthesis for Clock Skew Minimization
    Lee, Yu
    Huang, Shih-Hsu
    2017 INTERNATIONAL CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS (EDSSC), 2017,
  • [34] NOISE AWARE CLOCK TREE SYNTHESIS FOR 3D ICs
    Pan, Xiaofeng
    Xie, Jing
    Wang, Qin
    Mao, Zhigang
    2014 12TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT), 2014,
  • [35] Temperature Insensitive Clock Buffer and Its Application on Clock Tree
    Tie, Meng
    Li, Xia
    CHINA SEMICONDUCTOR TECHNOLOGY INTERNATIONAL CONFERENCE 2011 (CSTIC 2011), 2011, 34 (01): : 183 - 188
  • [36] Multisource Clock Tree Synthesis Through Sink Clustering and Fast Clock Latency Prediction
    Choi, Byungho
    Kwon, Yonghwi
    Afzaal, Umar
    Shin, Youngsoo
    2023 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, ISCAS, 2023,
  • [37] On Constructing Low Power and Robust Clock Tree via Slew Budgeting
    Chang, Yeh-Chi
    Wang, Chun-Kai
    Chen, Hung-Ming
    ISPD 12: PROCEEDINGS OF THE 2012 INTERNATIONAL SYMPOSIUM ON PHYSICAL DESIGN, 2012, : 129 - 135
  • [38] Iterative convergence of optimal wire sizing and available buffer insertion for zero-skew clock tree optimization
    Yan, JT
    Wu, CW
    Lin, KP
    Lee, YC
    Wang, TY
    PROCEEDINGS OF THE 2004 IEEE ASIA-PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS, VOL 1 AND 2: SOC DESIGN FOR UBIQUITOUS INFORMATION TECHNOLOGY, 2004, : 529 - 532
  • [39] Clock Tree Construction and Buffer Planning in Placement
    Liu, Renwei
    Cai, Yici
    Shen, Weixiang
    2009 INTERNATIONAL CONFERENCE ON COMMUNICATIONS, CIRCUITS AND SYSTEMS PROCEEDINGS, VOLUMES I & II: COMMUNICATIONS, NETWORKS AND SIGNAL PROCESSING, VOL I/ELECTRONIC DEVICES, CIRUITS AND SYSTEMS, VOL II, 2009, : 1037 - 1041
  • [40] WaveMin: A Fine-Grained Clock Buffer Polarity Assignment Combined with Buffer Sizing
    Joo, Deokjin
    Kim, Taewhan
    PROCEEDINGS OF THE 48TH ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC), 2011, : 522 - 527