This paper proposes the adaptive codeword error correcting code (ECC) for non-volatile random access memory (NV-RAM) and NAND flash memory-integrated solid state drive (SSD). In the proposed SSD, NV-RAM such as resistive random access memory (ReRAM), phase change random access memory (PRAM) and magneto resistive random access memory (MRAM) is used as write buffers. The NV-RAM write buffer compensates the 10-100 times speed gap between the NAND flash memory and the SSD interface and realizes the 10 Gbps write. During the write, data are first stored in NV-RAM at 10 Gbps. Then, data in NV-RAM are transferred to the NAND flash memory with the sustained write speed of 2.69 Gbps. During the read, the read data output from the NAND flash memory to the controller by bypassing NV-RAM. At the 10 Gbps write, the proposed SSD decreases the power consumption by 97%. In the proposed adaptive codeword ECC, errors of both NV-RAM and the NAND flash memory are corrected without circuit area overhead. The ECC codeword, the data unit where ECC is performed, is adaptively optimized for NV-RAM and the NAND flash memory. As a result, the acceptable raw bit error rate before ECC increases by 3.6 times without ECC circuit area or power consumption penalty compared with the single ECC scheme where the single ECC circuits correct errors of both NV-RAM and the NAND flash memory. (C) 2011 The Japan Society of Applied Physics
