Continuous time ΣΔ modulator based on digital delay loop and time quantisation

A new sigma delta (Sigma Delta) modulator suitable for ultra-low power data converters is introduced. The proposed architecture is based on time encoding and quantisation using voltage controlled delays such as digital inverters. The delays together with a phase comparator implement a synchronous pulse width modulator (PWM) and a discrete time integrator. An additional analogue integrator provides second-order noise shaping and compensates the nonlinearity of the digital delay. Time quantisation of the two-level PWM signal allows implementing a multibit modulator without requiring linear multibit DACs. counter counter