DESIGN AND IMPLEMENTATION OF EFFICIENT REVERSIBLE EVEN PARITY CHECKER AND GENERATOR

被引：0

作者：

Gayathri, S. S. ^{[1
]}

Ananthalakshmi, A. V. ^{[2
]}

机构：

[1] Dhanalakshmi Srinivasan Inst Res Technol, Dept ECE, Siruvachur, Tamil Nadu, India

[2] Pondicherry Engn Coll, Dept ECE, Pondicherry, India

来源：

2014 International Conference on Science Engineering and Management Research (ICSEMR) | 2014年

关键词：

Reversible logic; Parity checker and generator; Feynman gate; Toffoli gate; New gate; Peres gate;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Communication in today's world is made efficient by digital data transmission. The digital communication employs parity generator at the source and parity checker at destination to ensure an error free transmission. This paper proposes the design of a 3-bit reversible even parity checker and generator using the basic reversible gates. The parity checker and generator circuit is designed using the existing basic reversible gates like Feynman gate, Toffoli gate, Peres gate and New gate and the performance of the designed parity checker and generator is discussed. The proposed design is designed using Modelsim and synthesized using Xilinx Virtex5vlx30tff665-3.

引用

页数：4