Cell broadband engine processor design methodology

被引：0

作者：

Takahashi, O. ^{[1
]}

Behnen, E. ^{[1
]}

Cottier, S. R. ^{[1
]}

Coulman, P. ^{[1
]}

Dhong, S. H. ^{[1
]}

Flachs, B. ^{[1
]}

Hofstee, P. ^{[1
]}

Johnson, C. J. ^{[1
]}

Posluszny, S. ^{[1
]}

机构：

[1] IBM Syst & Technol Grp, Austin, TX USA

来源：

PROCEEDINGS OF THE IEEE 2007 CUSTOM INTEGRATED CIRCUITS CONFERENCE | 2007年

关键词：

D O I：

10.1109/CICC.2007.4405830

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The Cell BE design methodology is described which enables high frequency, high performance, power efficient, and area optimized design. It includes a hierarchical design style, clean clock boundary, effective use of non-scan latches, at-speed scan testing, custom design like synthesized macro, fine grained clock gating scheme, and cycle accurate power analysis.

引用

页码：711 / 716

页数：6

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