Motion compensation hardware accelerator architecture for H.264/AVC

被引：0
作者：
Zatt, Bruno [1 ]
Ferreira, Valter [1 ]
Agostini, Luciano [2 ]
Wagner, Flavio R. [1 ]
Susin, Altamiro [3 ]
Bampi, Sergio [1 ]
机构：
[1] Univ Fed Rio Grande do Sul, Inst Informat, Porto Alegre, RS, Brazil
[2] Univ Fed Pelotas, Informat Dept, Pelotas, RS, Brazil
[3] Univ Fed Rio Grande do Sul, Elect Engn Dept, Porto Alegre, RS, Brazil
来源：
ADVANCES IN IMAGE AND VIDEO TECHNOLOGY, PROCEEDINGS | 2007年 / 4872卷
关键词：
video coding; H.264/AVC; MPEG-4; AVC; motion compensation; hardware acceleration;
D O I：
暂无
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
This work presents a new hardware acceleration solution for the H.264/AVC motion compensation process. A novel architecture is proposed to precede the luminance interpolation task, which responds by the highest computational complexity in the motion compensator. The accelerator module was integrated into the VHDL description of the MIPS Plasma processor, and its validation was accomplished by simulation. A performance comparison was made between a software implementation and a hardware accelerated one. This comparison indicates a reduction of 94% in processing time. The obtained throughput is enough to reach real time when decoding H.264/AVC Baseline Profile motion compensation for luminance at Level 3.
引用
收藏
页码：24 / +
页数：2
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