Motion compensation hardware accelerator architecture for H.264/AVC

被引：0

作者：

Zatt, Bruno ^{[1
]}

Ferreira, Valter ^{[1
]}

Agostini, Luciano ^{[2
]}

Wagner, Flavio R. ^{[1
]}

Susin, Altamiro ^{[3
]}

Bampi, Sergio ^{[1
]}

机构：

[1] Univ Fed Rio Grande do Sul, Inst Informat, Porto Alegre, RS, Brazil

[2] Univ Fed Pelotas, Informat Dept, Pelotas, RS, Brazil

[3] Univ Fed Rio Grande do Sul, Elect Engn Dept, Porto Alegre, RS, Brazil

来源：

ADVANCES IN IMAGE AND VIDEO TECHNOLOGY, PROCEEDINGS | 2007年 / 4872卷

关键词：

video coding; H.264/AVC; MPEG-4; AVC; motion compensation; hardware acceleration;

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

This work presents a new hardware acceleration solution for the H.264/AVC motion compensation process. A novel architecture is proposed to precede the luminance interpolation task, which responds by the highest computational complexity in the motion compensator. The accelerator module was integrated into the VHDL description of the MIPS Plasma processor, and its validation was accomplished by simulation. A performance comparison was made between a software implementation and a hardware accelerated one. This comparison indicates a reduction of 94% in processing time. The obtained throughput is enough to reach real time when decoding H.264/AVC Baseline Profile motion compensation for luminance at Level 3.

引用

页码：24 / +

页数：2

共 50 条

[21] An H.264/AVC Decoder with Reduced External Memory Access for Motion Compensation
Kim, Jaesun
Kim, Younghoon
Lee, Hyuk-Jae
IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 2011, E94D (04): : 798 - 808
[22] Parallel Motion Compensation Interpolation in H.264/AVC using Graphic Processing Units
Zhang, Liye
Wang, Jian
Chu, Chen
Ji, Xiaoyong
2012 INTERNATIONAL CONFERENCE ON INDUSTRIAL CONTROL AND ELECTRONICS ENGINEERING (ICICEE), 2012, : 767 - 771
[23] Fractional-Pel Motion Compensation Interpolation Architecture Based on Parallel FIR Systolic Arrays for H.264/AVC
Ma, Liang
Du, Gao-Ming
Zhang, Duo-Li
Song, Yu-Kun
Geng, Luo-Feng
Gao, Ming-Lun
2008 2ND INTERNATIONAL CONFERENCE ON ANTI-COUNTERFEITING, SECURITY AND IDENTIFICATION, 2008, : 328 - 331
[24] Adaptive motion estimation algorithm for H.264/AVC
Momcilovic, Svetislay
Roma, Nuno
Sousa, Leonel
PROCEEDINGS OF THE 2007 15TH INTERNATIONAL CONFERENCE ON DIGITAL SIGNAL PROCESSING, 2007, : 519 - +
[25] On hardware implementations of DCT and quantization blocks for H.264/AVC
Kordasiewicz, Roman
Shirani, Shahram
JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, 2007, 47 (02): : 93 - 102
[26] Window architecture for deblocking filter in H.264/AVC
Chen, Chung-Ming
Zeng, Jian-Ping
Chen, Chung-Ho
Yu, Chao-Tang
Chang, Yu-Pin
2006 IEEE INTERNATIONAL SYMPOSIUM ON SIGNAL PROCESSING AND INFORMATION TECHNOLOGY, VOLS 1 AND 2, 2006, : 338 - +
[27] Window architecture for deblocking filter in H.264/AVC
Chen, Chung-Ming
Chen, Chung-Ho
INTERNATIONAL JOURNAL OF INNOVATIVE COMPUTING INFORMATION AND CONTROL, 2007, 3 (6B): : 1677 - 1695
[28] On Hardware Implementations Of DCT and Quantization Blocks for H.264/AVC
Roman Kordasiewicz
Shahram Shirani
The Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, 2007, 47 : 189 - 199
[29] On hardware implementations of DCT and quantization blocks for H.264/AVC
Kordasiewicz, Roman
Shirani, Shahram
JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, 2007, 47 (03): : 189 - 199
[30] On Hardware Implementations Of DCT and Quantization Blocks for H.264/AVC
Roman Kordasiewicz
Shahram Shirani
The Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, 2007, 47 : 93 - 102

← 1 2 3 4 5 →