Improved two-step clock-feedthrough compensation technique for switched-current circuits

被引：13

作者：

Helfenstein, M ^{[1
]}

Moschytz, GS ^{[1
]}

机构：

[1] Swiss Fed Inst Technol, Inst Signal & Informat Proc, CH-8092 Zurich, Switzerland

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | 1998年 / 45卷 / 06期

关键词：

analog sampled-data circuits; charge injection; sample/hold; switched-current circuits;

D O I：

10.1109/82.686693

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A new clock-feedthrough compensation scheme for switched-current circuits is proposed, The scheme is especially suited for the design of delay lines for high-frequency operation. The circuit operates by using an improved two-step technique, in which the input is sampled in a parallel combination of a coarse and a fine memory transistor. Since both transistors are of the same type, large switching transients compared to the conventional (SI)-I-2 scheme ran be avoided. Using the proposed circuit, the coarse memory has considerably more time to settle. Compared to the simple cell, the circuit solution requires only one extra switch and one additional clock phase.

引用

页码：739 / 743

页数：5

共 17 条

[1] A FAST-SETTLING CMOS OP AMP FOR SC CIRCUITS WITH 90-DB DC GAIN [J].

BULT, K ;

GEELEN, GJGM .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1990, 25 (06) :1379-1384

[2] CURRENT COPIER CELLS [J].

DAUBERT, SJ ;

VALLANCOURT, D ;

TSIVIDIS, YP .

ELECTRONICS LETTERS, 1988, 24 (25) :1560-1562

[3]

FIEZ TS, 1991, INT C CIRCUITS SYST, P785

[4] FIR SWITCHED-CAPACITOR DECIMATORS WITH ACTIVE-DELAYED BLOCK POLYPHASE STRUCTURES [J].

FRANCA, JE ;

SANTOS, S .

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, 1988, 35 (08) :1033-1037

[5] SWITCHED-CURRENT MEMORY-CIRCUITS FOR HIGH-PRECISION APPLICATIONS [J].

GUGGENBUHL, W ;

DI, JD ;

GOETTE, J .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1994, 29 (09) :1108-1116

[6] CLOCKFEEDTHROUGH COMPENSATION TECHNIQUE FOR SWITCHED-CURRENT CIRCUITS [J].

HELFENSTEIN, M ;

MOSCHYTZ, GS .

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 1995, 42 (03) :229-231

[7]

HELFENSTEIN M, 1996, P IEEE INT S CIRC SY, P195

[8]

Hughes J. B., 1993, [Proceedings] 1993 IEEE International Symposium on Circuits and Systems, P1235, DOI 10.1109/ISCAS.1993.393952

[9] CHARACTERIZATION AND MODELING OF MISMATCH IN MOS-TRANSISTORS FOR PRECISION ANALOG DESIGN [J].

LAKSHMIKUMAR, KR ;

HADAWAY, RA ;

COPELAND, MA .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1986, 21 (06) :1057-1066

[10]

LUESCHER RE, 1985, IEEE INT SOLID STATE, P260

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