A novel biasing technique for addressable parametric arrays

被引：6

作者：

Smith, Brad ^{[1
]}

Annamalai, Uma ^{[2
]}

Arriordaz, Alexandre ^{[1
]}

Kolagunta, Venkat ^{[1
]}

Schmidt, Jeff ^{[1
]}

Shroff, Mehul ^{[1
]}

机构：

[1] Freescale Semicond, 3501 Ed Bluestein Blvd Mailstop K-10, Austin, TX 78721 USA

[2] Univ Arkansas, Austin, TX 78721 USA

来源：

2008 IEEE INTERNATIONAL CONFERENCE ON MICROELECTRONIC TEST STRUCTURES, CONFERENCE PROCEEDINGS | 2008年

关键词：

D O I：

10.1109/ICMTS.2008.4509333

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Addressable arrays that use switches to isolate the devices being tested are limited in size and utility by the parasitic leakage caused by those switches. A new biasing technique that removes the drain-source bias from these switches has been studied to address this problem. Simulations performed in a 90 nm low-power technology predicted more than a two-decade drop in parasitic leakage of the array. Experiment data performed on a 90 nm technology confirmed this improvement.

引用

页码：166 / +

页数：3

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