Enhancing System-Wide Power Integrity in 3D ICs with Power Gating

被引:0
作者
Wang, Hailong [1 ]
Salman, Emre [1 ]
机构
[1] SUNY Stony Brook, Dept Elect & Comp Engn, Stony Brook, NY 11794 USA
来源
PROCEEDINGS OF THE SIXTEENTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED 2015) | 2015年
关键词
Power delivery; 3D IC; power gating; 3-D;
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Power gating is a commonly used method to reduce subthreshold leakage current in nanoscale technologies. In through silicon via (TSV) based three-dimensional (3D) integrated circuits (ICs), power gating can significantly degrade system-wide power integrity since the decoupling capacitance associated with the power gated block/plane becomes ineffective for neighboring active planes, as demonstrated in this paper. A reconfig-urable decoupling capacitor topology is investigated to alleviate this issue by exploiting the ability of via-last TSVs to bypass plane-level power networks when delivering the supply voltage. Reconfigurable decoupling capacitors placed within a plane can provide charge to neighboring planes even when the plane is power gated, thereby significantly reducing both RMS power supply noise (by up to 46%) and RMS power gating (in-rush current) noise (by up to 85%) at the expense of a slight increase in area (by 1.55%) and peak power consumption (by 1.36%).
引用
收藏
页码:322 / 326
页数:5
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