Realization of 850 V breakdown voltage LDMOS on Simbond SOI

In this paper, 850 V breakdown voltage LDMOS fabricated on Simbond SOI wafer are reported. Simbond SOI wafers with 1.5 mu m top silicon, 3 mu m buried oxide layer, and n-type heavy doped handle wafers are used. In order to achieve uniform lateral electric field and shorten the vertical impact ionization integration path simultaneously, an optimized 60 mu m drift region implant mask is designed to realize a linearly graded doping profile, and silicon thickness in the drift region is reduced from 1.5 mu m to about 0.26 mu m by thick field oxide process. CMOS compatible SOI LDMOS processes are designed and implemented successfully. Off-state breakdown voltage of SOI LDMOS can reach 850 V, and the specific on-resistance is 56 Omega mm(2). Experimental results also show the thickness of the top silicon in the drift region has a good uniformity. The performance of SOI LDMOS indicated that Simbond SOI wafers are good choice for thin film high voltage devices. (C) 2011 Elsevier B.V. All rights reserved.