Synthesis of optical circuits using binary decision diagrams

被引:6
|
作者
Deb, Arighna [1 ,2 ]
Wille, Robert [3 ,4 ]
Keszoecze, Oliver [1 ,4 ]
Shirinzadeh, Saeideh [1 ]
Drechsler, Rolf [1 ,4 ]
机构
[1] Univ Bremen, Inst Comp Sci, Bremen, Germany
[2] Jadavpur Univ, Comp Sci & Engn, Kolkata, India
[3] Johannes Kepler Univ Linz, Inst Integrated Circuits, Linz, Austria
[4] DFKI GmbH, Cyber Phys Syst, Bremen, Germany
关键词
Optical circuits; Synthesis; Optimization; Binary decision diagrams; XOR;
D O I
10.1016/j.vlsi.2017.05.001
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
The advances in silicon photonics motivated the consideration of optical circuits as a new and emerging circuit technology. In particular for ultra-fast interconnects, optical circuits may provide a suitable alternative since it avoids the conversion of signals from the optical to the electrical domain. Accordingly, design automation of this kind of circuits received significant attention. In this work, we consider synthesis of optical circuits based on Binary Decision Diagrams (BDDs). Although BDDs allow for a direct mapping of the function representation to an optical circuit (and, hence, a scalable synthesis), they have their shortcomings with respect to dedicated cost metrics. In this work, we investigate this issue and provide an overview of the BDD-based synthesis schemes which are available thus far. Afterwards, we propose new solutions based on a dedicated BDD optimization which aim for addressing the known shortcomings. Experimental results confirm the benefits of the proposed approach.
引用
收藏
页码:42 / 51
页数:10
相关论文
共 50 条
  • [41] Evolving binary decision diagrams using implicit neutrality
    Downing, RM
    2005 IEEE CONGRESS ON EVOLUTIONARY COMPUTATION, VOLS 1-3, PROCEEDINGS, 2005, : 2107 - 2113
  • [42] Using Datalog with binary decision diagrams for program analysis
    Whaley, J. (jwhaley@cs.stanford.edu), Asian Association for Foundation of Software; Japan Society for Software Science and Technology; International Information Science Foundation, Japan; University of Tsukuba (Springer Verlag):
  • [43] Synthesis of multiple-valued Decision Diagrams using current-mode CMOS circuits
    Abd-El-Barr, M
    Fernandes, H
    1999 29TH IEEE INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC, PROCEEDINGS, 1999, : 160 - 165
  • [44] Reversible Logic Synthesis via Biconditional Binary Decision Diagrams
    Chattopadhyay, Anupam
    Littarru, Alessandro
    Amaru, Luca
    Gaillardon, Pierre-Emmanuel
    De Micheli, Giovanni
    2015 IEEE 45TH INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC, 2015, : 2 - 7
  • [45] Zero-suppressed Binary Decision Diagrams Automated Test Assmbly using Zero-suppressed Binary Decision Diagrams
    Fuchimoto K.
    Minato S.-I.
    Ueno M.
    Transactions of the Japanese Society for Artificial Intelligence, 2022, 37 (05)
  • [46] Partial binary decision diagrams
    Townsend, WJ
    Thornton, MA
    PROCEEDINGS OF THE THIRTY-FOURTH SOUTHEASTERN SYMPOSIUM ON SYSTEM THEORY, 2002, : 422 - 425
  • [47] Equational binary decision diagrams
    Groote, JF
    van de Poll, J
    LOGIC FOR PROGRAMMING AND AUTOMATED REASONING, PROCEEDINGS, 2000, 1955 : 161 - 178
  • [48] A CHARACTERIZATION OF BINARY DECISION DIAGRAMS
    CHAKRAVARTY, S
    IEEE TRANSACTIONS ON COMPUTERS, 1993, 42 (02) : 129 - 137
  • [49] Timed binary decision diagrams
    Li, ZC
    Zhao, YH
    Min, YH
    Brayton, RK
    INTERNATIONAL CONFERENCE ON COMPUTER DESIGN - VLSI IN COMPUTERS AND PROCESSORS, PROCEEDINGS, 1997, : 352 - 357
  • [50] Compressing Binary Decision Diagrams
    Hansen, Esben Rune
    Rao, S. Srinivasa
    Tiedemann, Peter
    ECAI 2008, PROCEEDINGS, 2008, 178 : 799 - +