An FPGA based coprocessor for large matrix product implementation

被引：8

作者：

Bensaali, F ^{[1
]}

Amira, A ^{[1
]}

Bouridane, A ^{[1
]}

机构：

[1] Queens Univ Belfast, Belfast BT7 1NN, Antrim, North Ireland

来源：

2003 IEEE INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE TECHNOLOGY (FPT), PROCEEDINGS | 2003年

关键词：

D O I：

10.1109/FPT.2003.1275760

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Matrix multiplication is very important in many types of applications including image and signal processing. This paper presents an investigation into the design and implementation of matrix product algorithm using different design approaches such as Handel-C and VHDL, where the performances of both programming languages have been presented. Solutions for processing large matrix products based partitioning methodology have been described. The proposed system has been implemented and verified using the RC1000-PP Celoxica board based development platform.

引用

页码：292 / 295

页数：4

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