Improving circuit robustness with cost-effective soft-error-tolerant sequential elements

Soft errors induced by alpha particles and cosmic radiation have become a highly challenging problem in the design of UDSM or nanoscale circuits, making the incorporation of circuit hardening techniques essential. In this paper a design technique for soft-error-tolerant sequential elements is presented to improve circuit robustness. The proposed technique exploits time and space redundancy using an elaborate flip-flop structure, and provides complete soft error immunity for both the transient faults generated in the combinatorial logic and the particle strikes inside the flip-flops. The proposed technique is developed to be compatible with current digital design technology, thus having minimal impact on design flow and hardware cost. Simulation results confirm the effectiveness of the proposed technique.