Chip Design of a 24 GHz Band Low-Power Phase-Locked Loop Using an Injection Frequency Divider Circuit and Integrated system for Biomedical Application

A 21.6 GHz phase-locked loop (PLL) with a LC-tank voltage-controlled oscillates (VCO) is implemented in TSMC 90 nm CMOS 1P9M process. In this proposed circuit, two important ideas are applied. First, an all-nMOS cross-coupled Colpitts VCO is adopted to decrease the transistor parasitic capacitance and reduce the phase noise. Second, an injection locked frequency divider (ILFD) is utilized in first divider stage to handle the high frequency signal. Measured results achieve that at supply voltage of 1.2 V, the VCO output frequency is tunable from 21.54 similar to 21.96 GHz and the synthesizer phase noise is about -97.47 dBc/Hz at 1MHz offset from the carrier frequency of 21.68 GHz. The mixed output power spectrum is -2.97 dBm at 10.2 GHz and the power consumption is 9.24 mW. Including pads, the chip area is 0.8 x 1.0 mm(2).