Effects of traps on charge storage characteristics in metal-oxide-semiconductor memory structures based on silicon nanocrystals

被引:287
作者
Shi, Y
Saito, K
Ishikuro, H
Hiramoto, T
机构
[1] Univ Tokyo, Inst Ind Sci, Minato Ku, Tokyo 1068558, Japan
[2] Nanjing Univ, Dept Phys, Nanjing 210093, Peoples R China
[3] Univ Tokyo, VLSI Design & Educ Ctr, Bunkyo Ku, Tokyo 1138656, Japan
关键词
D O I
10.1063/1.368346
中图分类号
O59 [应用物理学];
学科分类号
摘要
Charge storage characteristics have been investigated in metal-oxide-semiconductor memory structures based on silicon nanocrystals, where various interface traps and defects were introduced by thermal annealing treatment. The observations demonstrate that traps have strong influence on the charge storage behavior, in which the traps and defects at the internal/surface of silicon nanocrystals and the interface states at the SiO2/Si substrate play different roles, respectively. It is suggested that the injected charges are mainly stored at the deep traps of nanocrystals instead of the conduction band in long-term retention mode. The long-term charge-loss process is dominantly determined by the direct tunneling of the trapped charges to the interface states in the present experiment. An optimum way to improve the retention time would be to introduce a certain number of deep trapping centers in nanocrystals and to decrease the interface states at SiO2/Si substrate. (C) 1998 American Institute of Physics. [S0021-8979(98)09216-0].
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页码:2358 / 2360
页数:3
相关论文
共 11 条
  • [1] CHARGE-TRANSFER BY DIRECT TUNNELING IN THIN-OXIDE MEMORY TRANSISTORS
    FERRISPRABHU, AV
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 1977, 24 (05) : 524 - 530
  • [2] A room-temperature silicon single-electron metal-oxide-semiconductor memory with nanoscale floating-gate and ultranarrow channel
    Guo, LJ
    Leobandung, E
    Chou, SY
    [J]. APPLIED PHYSICS LETTERS, 1997, 70 (07) : 850 - 852
  • [3] CHARGE RETENTION IN SCALED SONOS NONVOLATILE SEMICONDUCTOR MEMORY DEVICES - MODELING AND CHARACTERIZATION
    HU, Y
    WHITE, MH
    [J]. SOLID-STATE ELECTRONICS, 1993, 36 (10) : 1401 - 1416
  • [4] Verify: Key to the stable single-electron-memory operation
    Ishii, T
    Yano, K
    Sano, T
    Mine, T
    Murai, F
    Seki, K
    [J]. INTERNATIONAL ELECTRON DEVICES MEETING - 1997, TECHNICAL DIGEST, 1997, : 171 - 174
  • [5] Coulomb blockade oscillations at room temperature in a Si quantum wire metal-oxide-semiconductor field-effect transistor fabricated by anisotropic etching on a silicon-on-insulator substrate
    Ishikuro, H
    Fujii, T
    Saraya, T
    Hashiguchi, G
    Hiramoto, T
    Ikoma, T
    [J]. APPLIED PHYSICS LETTERS, 1996, 68 (25) : 3585 - 3587
  • [6] KOHNO A, 1997, INT C SOL STAT DEV M, P566
  • [7] Room temperature operation of Si single-electron memory with self-aligned floating dot gate
    Nakajima, A
    Futatsugi, T
    Kosemura, K
    Fukano, T
    Yokoyama, N
    [J]. IEDM - INTERNATIONAL ELECTRON DEVICES MEETING, TECHNICAL DIGEST 1996, 1996, : 952 - 954
  • [8] Single charge and confinement effects in nano-crystal memories
    Tiwari, S
    Rana, F
    Chan, K
    Shi, L
    Hanafi, H
    [J]. APPLIED PHYSICS LETTERS, 1996, 69 (09) : 1232 - 1234
  • [9] Tiwari S, 1996, APPL PHYS LETT, V68, P1377, DOI 10.1063/1.116085
  • [10] Conductance measurements on P-b centers at the (111)Si:SiO2 interface
    Uren, MJ
    Stathis, JH
    Cartier, E
    [J]. JOURNAL OF APPLIED PHYSICS, 1996, 80 (07) : 3915 - 3922