Annealing Temperature Optimization for High-Performance Carbon Nanotube Thin Film Transistors

The effect of annealing treatment on the device performance of carbon nanotube thin film transistors (CNT-TFTs) have been investigated systematically. The optimized annealing temperature has been found out from the tradeoff between source-drain total resistance and on-off current ratio, resulting in high-performance CNT-TFTs with a typical I-on/I-off larger than 10(6), a subthreshold swing as low as 140 mV/dec and a threshold voltage of -0.2 V. When the annealing temperature increased from 300 degrees C to 400 degrees C, the device mobility reached 9.7 cm(2)/vs while I-on/I-off decreased to 10(5). After annealing of 450 degrees C or above, the off current increased abruptly due to the appearance of metallic nanotube pathways, which can be improved by the electrical breakdown.