Observing the Invisible: Live Cache Inspection for High-Performance Embedded Systems

被引:3
|
作者
Tarapore, Dharmesh [1 ]
Roozkhosh, Shahin [1 ]
Brzozowski, Steven [1 ]
Mancuso, Renato [1 ]
机构
[1] Boston Univ, Boston, MA 02215 USA
基金
美国国家科学基金会;
关键词
Hardware; Software; Program processors; Central Processing Unit; Random access memory; Phasor measurement units; Analytical models; Cache; cache snapshotting; ramindex; cacheflow; cache debugging; SIMULATION;
D O I
10.1109/TC.2021.3060650
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
The vast majority of high-performance embedded systems implement multi-level CPU cache hierarchies. But the exact behavior of these CPU caches has historically been opaque to system designers. Absent expensive hardware debuggers, an understanding of cache makeup remains tenuous at best. This enduring opacity further obscures the complex interplay among applications and OS-level components, particularly as they compete for the allocation of cache resources. Notwithstanding the relegation of cache comprehension to proxies such as static cache analysis, performance counter-based profiling, and cache hierarchy simulations, the underpinnings of cache structure and evolution continue to elude software-centric solutions. In this article, we explore a novel method of studying cache contents and their evolution via snapshotting. Our method complements extant approaches for cache profiling to better formulate, validate, and refine hypotheses on the behavior of modern caches. We leverage cache introspection interfaces provided by vendors to perform live cache inspections without the need for external hardware. We present CacheFlow, a proof-of-concept Linux kernel module which snapshots cache contents on an NVIDIA Tegra TX1 system on chip and a Hardkernel Odroid XU4.
引用
收藏
页码:559 / 572
页数:14
相关论文
共 41 条
  • [41] FT-PBLAS: PBLAS-Based Fault-Tolerant Linear Algebra Computation on High-performance Computing Systems
    Zhu, Yanchao
    Liu, Yi
    Zhang, Guozhen
    IEEE ACCESS, 2020, 8 : 42674 - 42688