Observing the Invisible: Live Cache Inspection for High-Performance Embedded Systems

被引:3
|
作者
Tarapore, Dharmesh [1 ]
Roozkhosh, Shahin [1 ]
Brzozowski, Steven [1 ]
Mancuso, Renato [1 ]
机构
[1] Boston Univ, Boston, MA 02215 USA
基金
美国国家科学基金会;
关键词
Hardware; Software; Program processors; Central Processing Unit; Random access memory; Phasor measurement units; Analytical models; Cache; cache snapshotting; ramindex; cacheflow; cache debugging; SIMULATION;
D O I
10.1109/TC.2021.3060650
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
The vast majority of high-performance embedded systems implement multi-level CPU cache hierarchies. But the exact behavior of these CPU caches has historically been opaque to system designers. Absent expensive hardware debuggers, an understanding of cache makeup remains tenuous at best. This enduring opacity further obscures the complex interplay among applications and OS-level components, particularly as they compete for the allocation of cache resources. Notwithstanding the relegation of cache comprehension to proxies such as static cache analysis, performance counter-based profiling, and cache hierarchy simulations, the underpinnings of cache structure and evolution continue to elude software-centric solutions. In this article, we explore a novel method of studying cache contents and their evolution via snapshotting. Our method complements extant approaches for cache profiling to better formulate, validate, and refine hypotheses on the behavior of modern caches. We leverage cache introspection interfaces provided by vendors to perform live cache inspections without the need for external hardware. We present CacheFlow, a proof-of-concept Linux kernel module which snapshots cache contents on an NVIDIA Tegra TX1 system on chip and a Hardkernel Odroid XU4.
引用
收藏
页码:559 / 572
页数:14
相关论文
共 41 条
  • [21] A high-performance computing method for data allocation in distributed database systems
    Hababeh, Ismail Omar
    Ramachandran, Muthu
    Bowring, Nicholas
    JOURNAL OF SUPERCOMPUTING, 2007, 39 (01) : 3 - 18
  • [22] Agent-based High-Performance Simulation of Biological Systems on the GPU
    Konur, Savas
    Kiran, Mariam
    Gheorghe, Marian
    Burkitt, Mark
    Ipate, Florentin
    2015 IEEE 17TH INTERNATIONAL CONFERENCE ON HIGH PERFORMANCE COMPUTING AND COMMUNICATIONS, 2015 IEEE 7TH INTERNATIONAL SYMPOSIUM ON CYBERSPACE SAFETY AND SECURITY, AND 2015 IEEE 12TH INTERNATIONAL CONFERENCE ON EMBEDDED SOFTWARE AND SYSTEMS (ICESS), 2015, : 84 - 89
  • [23] Evaluating the SAT problem on P systems for different high-performance architectures
    Cecilia, Jose M.
    Garcia, Jose M.
    Guerrero, Gines D.
    Ujaldon, Manuel
    JOURNAL OF SUPERCOMPUTING, 2014, 69 (01) : 248 - 272
  • [24] A Technology of Full Seismic Field Simulation on High-performance Computing Systems
    Karavaev, Dmitry A.
    Yakimenko, Alexander A.
    Bulavina, Nina A.
    2016 13TH INTERNATIONAL SCIENTIFIC-TECHNICAL CONFERENCE ON ACTUAL PROBLEMS OF ELECTRONIC INSTRUMENT ENGINEERING (APEIE), VOL 2, 2016, : 439 - 442
  • [25] Design of a High-Performance Iterative Barrett Modular Multiplier for Crypto Systems
    Zhang, Bo
    Cheng, Zeming
    Pedram, Massoud
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2024, 32 (05) : 897 - 910
  • [26] Kriging-Based Design for Robust High-Performance Control Systems
    Micheli, Laura
    Laflamme, Simon
    ASCE-ASME JOURNAL OF RISK AND UNCERTAINTY IN ENGINEERING SYSTEMS PART A-CIVIL ENGINEERING, 2020, 6 (04)
  • [27] A high-performance computing method for data allocation in distributed database systems
    Ismail Omar Hababeh
    Muthu Ramachandran
    Nicholas Bowring
    The Journal of Supercomputing, 2007, 39 : 3 - 18
  • [28] A High-Performance Double-Layer Counting Bloom Filter for Multicore Systems
    Lai, Bo-Cheng Charles
    Chen, Kuan-Ting
    Wu, Ping-Ru
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2015, 23 (11) : 2473 - 2486
  • [29] A survey of software techniques to emulate heterogeneous memory systems in high-performance computing
    Foyer, Clement
    Goglin, Brice
    Proano, Andres Rubio
    PARALLEL COMPUTING, 2023, 116
  • [30] A high-performance/low-power on-chip memory-path architecture with variable cache-line size
    Inoue, K
    Kai, K
    Murakami, K
    IEICE TRANSACTIONS ON ELECTRONICS, 2000, E83C (11): : 1716 - 1723