An 11-bit 45 MS/s pipelined ADC with rapid calibration of DAC errors in a multibit pipeline stage

被引：55
作者：
Ahmed, Imran [1 ]
Johns, David A. [1 ]
机构：
[1] Univ Toronto, Dept Elect & Comp Engn, Toronto, ON M5S 3G4, Canada
来源：
IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2008年 / 43卷 / 07期
关键词：
ADC; analog-to-digital conversion; background; calibration; capacitor mismatch; CMOS; DAC; dual-ADC; missing codes; pipeline; rapid; split-ADC;
D O I：
10.1109/JSSC.2008.923724
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A technique to rapidly correct for both DAC and gain errors in the multibit first stage of an 11-bit pipelined ADC is presented. Using a dual-ADC based approach the digital background scheme is validated with a proof-of-concept prototype fabricated in a 1.8 V 0.18 mu m CMOS process, where the calibration scheme improves the peak INL of the 45 MS/s ADC from 6.4 LSB to 1.1 LSB after calibration. The SNDR/SFDR is improved from 46.9 dB/48.9 dB to 60.1 dB/70 dB after calibration. Calibration is achieved in approximately 10(4) clock cycles.
引用
收藏
页码：1626 / 1637
页数：12
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