An 11-bit 45 MS/s pipelined ADC with rapid calibration of DAC errors in a multibit pipeline stage

被引：55
作者：
Ahmed, Imran [1 ]
Johns, David A. [1 ]
机构：
[1] Univ Toronto, Dept Elect & Comp Engn, Toronto, ON M5S 3G4, Canada
来源：
IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2008年 / 43卷 / 07期
关键词：
ADC; analog-to-digital conversion; background; calibration; capacitor mismatch; CMOS; DAC; dual-ADC; missing codes; pipeline; rapid; split-ADC;
D O I：
10.1109/JSSC.2008.923724
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A technique to rapidly correct for both DAC and gain errors in the multibit first stage of an 11-bit pipelined ADC is presented. Using a dual-ADC based approach the digital background scheme is validated with a proof-of-concept prototype fabricated in a 1.8 V 0.18 mu m CMOS process, where the calibration scheme improves the peak INL of the 45 MS/s ADC from 6.4 LSB to 1.1 LSB after calibration. The SNDR/SFDR is improved from 46.9 dB/48.9 dB to 60.1 dB/70 dB after calibration. Calibration is achieved in approximately 10(4) clock cycles.
引用
收藏
页码：1626 / 1637
页数：12
相关论文
共 20 条
  • [1] An 11-bit 45MS/s pipelined ADC with rapid calibration of DAC errors in a multi-bit pipeline stage
    Ahmed, Imran
    Johns, David A.
    [J]. ESSCIRC 2007: PROCEEDINGS OF THE 33RD EUROPEAN SOLID-STATE CIRCUITS CONFERENCE, 2007, : 147 - 150
  • [2] A FAST-SETTLING CMOS OP AMP FOR SC CIRCUITS WITH 90-DB DC GAIN
    BULT, K
    GEELEN, GJGM
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1990, 25 (06) : 1379 - 1384
  • [3] Radix-based digital calibration techniques for multi-stage recycling pipelined ADCs
    Chang, DY
    Li, JP
    Moon, UK
    [J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2004, 51 (11) : 2133 - 2140
  • [4] Least mean square adaptive digital background calibration of pipelined analog-to-digital converters
    Chiu, Y
    Tsang, CW
    Nikolic, B
    Gray, PR
    [J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2004, 51 (01): : 38 - 46
  • [5] A 12-b digital-background-calibrated algorithmic ADC with-90-dB THD
    Erdogan, OE
    Hurst, PJ
    Lewis, SH
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1999, 34 (12) : 1812 - 1820
  • [6] Digital cancellation of D/A converter noise in pipelined A/D converters
    Galton, I
    [J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING, 2000, 47 (03): : 185 - 196
  • [7] A 12b 80MS/s pipelined ADC with bootstrapped digital calibration
    Grace, CR
    Hurst, PJ
    Lewis, SH
    [J]. 2004 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE, DIGEST OF TECHNICAL PAPERS, 2004, 47 : 460 - 461
  • [8] Johns D.A., 2008, Analog integrated circuit design
  • [9] A 15-b, 5-Msample/s low-spurious CMOS ADC
    Kwak, SU
    Song, BS
    Bacrania, K
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1997, 32 (12) : 1866 - 1875
  • [10] Power optimization for pipeline analog-to-digital converters
    Kwok, PTF
    Luong, HC
    [J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 1999, 46 (05) : 549 - 553
12