共 50 条
- [1] Fault characterization and testability considerations in Multi-Valued logic circuits 1999 29TH IEEE INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC, PROCEEDINGS, 1999, : 262 - 267
- [2] Possibility of combined use of neuron-MOS and RTD in multi-valued logic circuits 2003 5TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS, 2003, : 1357 - 1360
- [4] Satisfiability in multi-valued circuits LICS'18: PROCEEDINGS OF THE 33RD ANNUAL ACM/IEEE SYMPOSIUM ON LOGIC IN COMPUTER SCIENCE, 2018, : 550 - 558
- [5] Secure Design Flow for Asynchronous Multi-Valued Logic Circuits 40TH IEEE INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC ISMVL 2010, 2010, : 264 - 269
- [6] Three dimensional multi-valued design in nanoscale integrated circuits 35TH INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC, PROCEEDINGS, 2005, : 82 - 87
- [7] Modeling multi-valued circuits in SystemC 33RD INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC, PROCEEDINGS, 2003, : 281 - 286
- [8] Multi-valued simulation of digital circuits 1997 21ST INTERNATIONAL CONFERENCE ON MICROELECTRONICS - PROCEEDINGS, VOLS 1 AND 2, 1997, : 721 - 724
- [9] Basic circuits for multi-valued sequential logic Analog Integrated Circuits and Signal Processing, 2013, 74 : 91 - 96