A Low-Power High-Speed 16T 1-Bit Hybrid Full Adder

The paper presents a new model of low power 1-bit hybrid adder that uses CMOS and Transmission gate technologies together and produces full swing outputs. This adder is compared with the existing Conventional-CMOS (C-CMOS), CPL, TGA, 14T, 24T hybrid adder and 16T hybrid adder in terms of power, delay and power-delay product in 180-nm and 65-nm technology. The simulations were carried on for different voltages and frequencies on the Cadence Virtuoso using the Spectre simulator. The results conclude that the proposed adder consumes 35-40% low power compared to C-CMOS and is 25-50% faster than C-CMOS.