A Low-Power High-Speed 16T 1-Bit Hybrid Full Adder

被引：0

作者：

Agrawal, Priya ^{[1
]}

Raghuvanshi, D. K. ^{[1
]}

Gupta, M. K. ^{[1
]}

机构：

[1] MANIT, Elect & Comm Engn, Bhopal, India

来源：

2017 INTERNATIONAL CONFERENCE ON RECENT INNOVATIONS IN SIGNAL PROCESSING AND EMBEDDED SYSTEMS (RISE) | 2017年

关键词：

full adder; hybrid design; low power; high speed; cadence;

D O I：

暂无

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

The paper presents a new model of low power 1-bit hybrid adder that uses CMOS and Transmission gate technologies together and produces full swing outputs. This adder is compared with the existing Conventional-CMOS (C-CMOS), CPL, TGA, 14T, 24T hybrid adder and 16T hybrid adder in terms of power, delay and power-delay product in 180-nm and 65-nm technology. The simulations were carried on for different voltages and frequencies on the Cadence Virtuoso using the Spectre simulator. The results conclude that the proposed adder consumes 35-40% low power compared to C-CMOS and is 25-50% faster than C-CMOS.

引用

页码：348 / 352

页数：5

共 50 条

[1] Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit
Bhattacharyya, Partha
Kundu, Bijoy
Ghosh, Sovan
Kumar, Vinay
Dandapat, Anup
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2015, 23 (10) : 2001 - 2008
[2] Ultra Low-Power High-Speed Single-Bit Hybrid Full Adder Circuit
Kumar, Manoj
Baghel, R. K.
2017 8TH INTERNATIONAL CONFERENCE ON COMPUTING, COMMUNICATION AND NETWORKING TECHNOLOGIES (ICCCNT), 2017,
[3] Low-power and high-performance 1-bit set Full-adder
Paulthurai, Anbarasu
Dharmaraj, Balamurugan
INTERNATIONAL JOURNAL OF NANOELECTRONICS AND MATERIALS, 2013, 6 (02): : 105 - 111
[4] Design of a Scalable Low-Power 1-Bit Hybrid Full Adder for Fast Computation
Hasan, Mehedi
Hossein, Md. Jobayer
Hossain, Mainul
Zaman, Hasan U.
Islam, Sharnali
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2020, 67 (08) : 1464 - 1468
[5] Performance analysis of low-power 1-bit CMOS full adder cells
Shams, AM
Darwish, TK
Bayoumi, MA
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2002, 10 (01) : 20 - 29
[6] Low-power, high-speed 1-bit inexact Full Adder cell designs applicable to low-energy image processing
Zareei, Zahra
Navi, Keivan
Keshavarziyan, Peiman
INTERNATIONAL JOURNAL OF ELECTRONICS, 2018, 105 (03) : 375 - 384
[7] A Survey on Different Modules of Low-Power High-Speed Hybrid Full Adder Circuits
Saraswat, Vivek
Kumar, Ankur
Pal, Pratosh Kumar
Nagaria, R. K.
2017 4TH IEEE UTTAR PRADESH SECTION INTERNATIONAL CONFERENCE ON ELECTRICAL, COMPUTER AND ELECTRONICS (UPCON), 2017, : 323 - 328
[8] Symmetrical, Low-Power, and High-Speed 1-Bit Full Adder Cells Using 32nm Carbon Nanotube Field-effect Transistors Technology
Shafiabadi, M. H.
Mehrabani, Y. Safaei
INTERNATIONAL JOURNAL OF ENGINEERING, 2015, 28 (10): : 1447 - 1454
[9] A low-power high-speed hybrid multi-threshold full adder design in CNFET technology
Mojtaba Maleknejad
Somayyeh Mohammadi
Seyed Mostafa Mirhosseini
Keivan Navi
Hamid Reza Naji
Mehdi Hosseinzadeh
Journal of Computational Electronics, 2018, 17 : 1257 - 1267
[10] A low-power high-speed hybrid CMOS full adder for embedded system
Tung, Chiou-Kou
Hung, Yu-Cherng
Shieh, Shao-Hui
Huang, Guo-Shing
PROCEEDINGS OF THE 2007 IEEE WORKSHOP ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITS AND SYSTEMS, 2007, : 199 - +

← 1 2 3 4 5 →