A Low-Power High-Speed 16T 1-Bit Hybrid Full Adder

被引：0

作者：

Agrawal, Priya ^{[1
]}

Raghuvanshi, D. K. ^{[1
]}

Gupta, M. K. ^{[1
]}

机构：

[1] MANIT, Elect & Comm Engn, Bhopal, India

来源：

2017 INTERNATIONAL CONFERENCE ON RECENT INNOVATIONS IN SIGNAL PROCESSING AND EMBEDDED SYSTEMS (RISE) | 2017年

关键词：

full adder; hybrid design; low power; high speed; cadence;

D O I：

暂无

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

The paper presents a new model of low power 1-bit hybrid adder that uses CMOS and Transmission gate technologies together and produces full swing outputs. This adder is compared with the existing Conventional-CMOS (C-CMOS), CPL, TGA, 14T, 24T hybrid adder and 16T hybrid adder in terms of power, delay and power-delay product in 180-nm and 65-nm technology. The simulations were carried on for different voltages and frequencies on the Cadence Virtuoso using the Spectre simulator. The results conclude that the proposed adder consumes 35-40% low power compared to C-CMOS and is 25-50% faster than C-CMOS.

引用

页码：348 / 352

页数：5

共 12 条

[1]

Bhattacharyya P., 2015, IEEE T VERY LARGE SC, V23, P1

[2] A review of 0.18-μm full adder performances for tree structured arithmetic circuits [J].