Dipole Controlled Metal Gate with Hybrid Low Resistivity Cladding for Gate-Last CMOS with Low Vt

被引:12
作者
Hinkle, C. L. [1 ]
Galatage, R. V. [1 ]
Chapman, R. A. [1 ]
Vogel, E. M. [1 ]
Alshareef, H. N. [2 ]
Freeman, C. [3 ]
Wimmer, E. [3 ]
Niimi, H. [4 ]
Li-Fatou, A. [4 ]
Shaw, J. B. [4 ]
Chambers, J. J. [4 ]
机构
[1] Univ Texas Dallas, Dept Mat Sci & Engn, Richardson, TX 75080 USA
[2] King Abdullah Univ Sci & Technol, Thuwal, Saudi Arabia
[3] Mat Design Inc, Angel Fire, NM 87710 USA
[4] Texas Instruments Inc, Adv CMOS, Dallas, TX 75243 USA
来源
2010 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS | 2010年
关键词
D O I
10.1109/VLSIT.2010.5556220
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this contribution, NMOS and PMOS band edge effective work function (EWF) and correspondingly low Vt are demonstrated using standard fab materials and processes in a gate-last scheme. For NMOS, the use of an Al cladding layer results in Vt = 0.08 V consistent with NMOS EWF = 4.15 eV. Migration of the Al cladding into the TiN and a relatively low oxygen concentration near the TiN/HfO2 interface are responsible for the low EWF. For PMOS, employing a W cladding layer along with a post-TiN anneal in an oxidizing ambient results in elevated oxygen concentration near the TiN/HfO2 interface and Vt = -0.20 V consistent with a PMOS EWF = 5.05 eV. First-principles calculations indicate N atoms displaced from the TiN during the oxidizing anneal form dipoles at the TiN/HfO2 interface that play a critical role in determining the PMOS EWF.
引用
收藏
页码:183 / +
页数:2
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