On the timing uncertainty in delay-line-based time measurement applications targeting FPGAs

this paper addresses important performance issues in delay line-based timing applications targeting FPGA devices. The circuit under test is a TDC circuit implemented on a low-cost FPGA from XILINX Various performance limitations such as uncertainty and non-uniformity in cell delays are described and corresponding optimization and improvement suggestions are made. Experimental results were obtained using ring oscillator-based test structures to inspect intra-die delay mismatches along the target FPGA's surface.