Correction factors to strength of thin silicon die in three- and four-point bending tests due to nonlinear effects

被引:5
作者
Tsai, M. Y. [1 ]
Huang, P. S. [2 ]
机构
[1] Chang Gung Univ, Dept Mech Engn, Taoyuan, Taiwan
[2] MediaTek Inc, Hsinchu, Taiwan
关键词
Three-point bending; Four-point bending; Thin die; Bending strength; Geometric nonlinearity; LARGE DEFLECTIONS; FRICTION; WAFER;
D O I
10.1016/j.microrel.2021.114424
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The thin silicon dies have been widely used in the three-dimensional integrated circuits (3DIC), stacked-die or wearable electronic packages to meet the requirements of small size, low-profile features, high-pin count, high performance, low-power consumption or even flexibility. The bending strengths of the thin dies cut from silicon wafers have to be determined to ensure no reliability problems, mostly resulting from packaging process handling, reliability testing, and operations. Three-point bending (3PB) and four-point bending (4PB) tests are commonly used for measuring die bending strength; however, both tests are still problematic for testing the thin silicon dies. Therefore, the mechanics of both tests are reevaluated in this study by a nonlinear finite element method (NFEM) with taking into account geometric nonlinearity (or large deflection), associated with the related theoretical formulations. The nonlinear mechanics of both tests are discussed in detail. NFEM results-based correction factors to the linear beam solutions are further proposed in the form of the polynomial fitting equations in this study. Those polynomial fitting equations of the correction factors are proved to be workable and easy to use with an engineering acceptable accuracy. Those correction factors are also found highly dependent on the deflection (delta), span length (L) and radius of roller support (r), but not on test specimen thickness (t) and elastic modulus (E).
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页数:11
相关论文
共 28 条
[1]  
[Anonymous], 2013, C67413 ASTM
[2]  
[Anonymous], 2003, SEMI G86-0303 Standard
[3]  
[Anonymous], 2010, D627210 ASTM
[4]  
[Anonymous], 2003, ASTM D-790
[6]  
Burghartz JN, 2011, ULTRA-THIN CHIP TECHNOLOGY AND APPLICATIONS, P1, DOI 10.1007/978-1-4419-7276-7
[7]  
Conway H.D., 1947, PHILOS MAG, V38, P905
[8]  
Gambino JP, 2013, PROCEEDINGS OF THE 2013 20TH IEEE INTERNATIONAL SYMPOSIUM ON THE PHYSICAL & FAILURE ANALYSIS OF INTEGRATED CIRCUITS (IPFA 2013), P199, DOI 10.1109/IPFA.2013.6599153
[9]  
Gere J.M., 2001, MECH MATER
[10]   Thinning and singulation of silicon Root causes of the damage in thin chips [J].
Kroeninger, Werner ;
Mariani, Franco .
56TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE 2006, VOL 1 AND 2, PROCEEDINGS, 2006, :1317-+