HIGH VOLTAGE NLDMOS WITH MULTIPLE-RESURF STRUCTURE TO ACHIEVE IMPROVED ON-RESISTANCE

被引:0
|
作者
Yang, Shao-Ming [1 ]
Hema, E. P. [1 ]
Mrinal, Aryadeep [1 ]
Amanullah, Md [1 ]
Sheu, Gene [1 ]
Chen, P. A. [2 ]
机构
[1] Asia Univ, Dept Comp Sci & Informat Engn, 500 Lioufeng Rd, Taichung 41354, Taiwan
[2] Nuvoton Technol Corp, Taichung, Taiwan
来源
2015 China Semiconductor Technology International Conference | 2015年
关键词
LDMOS;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this paper, we present high voltage NLDMOS structure with multiple RSEURF concepts. The NLDMOS is based on 0.35 mu m BCD process. The multiple RESURF device base on charge balance theory using P-top and N-top to achieve high breakdown voltage and low on-resistance. The 2D simulation result compares the conventional single RESURF NLDMOS structure and the new structure with multiple RESURF devices. The new device concept help to improve the on-resistance up to 20% were as keeping the breakdown voltage still in the acceptable range for 40V rated device. The 2D simulation is using by process simulator Tsuprem4 and Medici to verify the device concept and identify the electrical characteristics.
引用
收藏
页数:3
相关论文
共 10 条
  • [1] Optimization of NLDMOS Structure for Higher Breakdown Voltage and Lower On-Resistance
    Hema, E. P.
    Sheu, Gene
    Aryadeep, M.
    Kurniawan, Erry Dwi
    Yang, S. M.
    Chen, P. A.
    2014 IEEE 8TH INTERNATIONAL POWER ENGINEERING AND OPTIMIZATION CONFERENCE (PEOCO), 2014, : 150 - 153
  • [2] Optimized Layout for Lateral Power Device with Improved Tradeoff between High Voltage and Low On-resistance
    Wei, Jie
    Dai, Kaiwei
    Ma, Zhen
    Luo, Xiaorong
    6TH IEEE ELECTRON DEVICES TECHNOLOGY AND MANUFACTURING CONFERENCE (EDTM 2022), 2022, : 36 - 38
  • [3] Analytical Model and New Structure of the Variable-k Dielectric Trench LDMOS With Improved Breakdown Voltage and Specific ON-Resistance
    Zhou, Kun
    Luo, Xiaorong
    Li, Zhaoji
    Zhang, Bo
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2015, 62 (10) : 3334 - 3340
  • [4] An ultralow on-resistance high-voltage SOI p-channel LDMOS
    Deng, Gaoqiang
    Wei, Jie
    Liu, Jianping
    Luo, Xiaorong
    SUPERLATTICES AND MICROSTRUCTURES, 2016, 100 : 1029 - 1041
  • [5] Novel high- with low specific on-resistance high voltage lateral double-diffused MOSFET
    吴丽娟
    章中杰
    宋月
    杨航
    胡利民
    袁娜
    Chinese Physics B, 2017, (02) : 386 - 390
  • [6] Novel high-K with low specific on-resistance high voltage lateral double-diffused MOSFET
    Wu, Li-Juan
    Zhang, Zhong-Jie
    Song, Yue
    Yang, Hang
    Hu, Li-Min
    Yuan, Na
    CHINESE PHYSICS B, 2017, 26 (02)
  • [7] Simulation study of an ultra-low specific on-resistance high-voltage pLDMOS with self-biased accumulation layer
    Yi, Bo
    Peng, Yi Feng
    Zhao, Qing
    Kong, MouFu
    Cheng, JunJi
    Huang, HaiMeng
    IEICE ELECTRONICS EXPRESS, 2020, 17 (02): : 1 - 4
  • [8] Effect of gate voltage on hot-carrier-induced on-resistance degradation in high-voltage n-type lateral diffused metal-oxide-semiconductor transistors
    Chen, Shiang-Yu
    Chen, Jone F.
    Wu, Kuo-Ming
    Lee, J. R.
    Liu, C. A.
    Hsu, S. L.
    JAPANESE JOURNAL OF APPLIED PHYSICS, 2008, 47 (04) : 2645 - 2649
  • [9] An Improved Robust Infinitely Differentiable Drift Resistance Model for BSIM High Voltage Compact Model
    Singhal, Anant
    Gill, Garima
    Pahwa, Girish
    Hu, Chenming
    Agarwal, Harshit
    2023 7TH IEEE ELECTRON DEVICES TECHNOLOGY & MANUFACTURING CONFERENCE, EDTM, 2023,
  • [10] P-channel lateral double-diffused metal-oxide-semiconductor field-effect transistor with split N-type buried layer for high breakdown voltage and low specific on-resistance
    Liaw, Chorng-Wei
    Chang, Ching-Hung
    Lin, Ming-Jang
    King, Ya-Ching
    Hsu, Charles Ching-Hsiang
    Lin, Chrong Jung
    JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS, 2007, 46 (7A): : 4046 - 4049