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- [1] Optimization of NLDMOS Structure for Higher Breakdown Voltage and Lower On-Resistance 2014 IEEE 8TH INTERNATIONAL POWER ENGINEERING AND OPTIMIZATION CONFERENCE (PEOCO), 2014, : 150 - 153
- [2] Optimized Layout for Lateral Power Device with Improved Tradeoff between High Voltage and Low On-resistance 6TH IEEE ELECTRON DEVICES TECHNOLOGY AND MANUFACTURING CONFERENCE (EDTM 2022), 2022, : 36 - 38
- [7] Simulation study of an ultra-low specific on-resistance high-voltage pLDMOS with self-biased accumulation layer IEICE ELECTRONICS EXPRESS, 2020, 17 (02): : 1 - 4
- [9] An Improved Robust Infinitely Differentiable Drift Resistance Model for BSIM High Voltage Compact Model 2023 7TH IEEE ELECTRON DEVICES TECHNOLOGY & MANUFACTURING CONFERENCE, EDTM, 2023,
- [10] P-channel lateral double-diffused metal-oxide-semiconductor field-effect transistor with split N-type buried layer for high breakdown voltage and low specific on-resistance JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS, 2007, 46 (7A): : 4046 - 4049