A scalable 5-15Gbps, 14-75mW low power I/O transceiver in 65nm CMOS

被引：20

作者：

Balamurugan, Ganesh ^{[1
]}

Kennedy, Joseph ^{[1
]}

Banerjee, Gaurab ^{[1
]}

Jaussi, James E. ^{[1
]}

Mansuri, Mozhgan ^{[1
]}

O'Mahony, Frank ^{[1
]}

Casper, Bryan ^{[1
]}

Mooney, Randy ^{[1
]}

机构：

[1] Intel Corp, Hillsboro, OR 97124 USA

来源：

2007 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS | 2007年

关键词：

I/O; parallel link; scalable circuits; low power; power management;

D O I：

10.1109/VLSIC.2007.4342746

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a scalable low power I/O transceiver in 65nm CMOS capable of 5-15Gbps operation over 8 '' FR4 with power efficiencies between 3-5mW/Gbps. Nonlinear power-performance tradeoff is achieved by the use of scalable transceiver circuit blocks and joint optimization of the supply voltage, bias currents and driver power. Low power operation is enabled by passive equalization through inductive link termination. active continuous-time RX equalization, global TX/RX clock distribution with on-die transmission lines, and low noise offset-calibrated receivers.

引用

页码：270 / 271

页数：2

共 5 条

[1]

Casper B., 2006, ISSCC 2006, P18

[2] A 4-Gb/s/pin low-power memory I/O interface using 4-level simultaneous bi-directional signaling [J].