IMPLEMENTATION OF MATCH FILTERS AS IP CORE FOR SONAR APPLICATIONS

被引:0
|
作者
Karabalkan, Melike Atay [1 ]
Oner, Mehmet [1 ]
机构
[1] ODTU TEKNOKENT, Koc Bilgi & Savunma Teknol, Ankara, Turkey
来源
2015 23RD SIGNAL PROCESSING AND COMMUNICATIONS APPLICATIONS CONFERENCE (SIU) | 2015年
关键词
FPGA; Match Filtering; Sonar; IP Core;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Matched Filtering is an important part of the radar and sonar systems. Implementation of match filtering in time or frequency domain can be more advantageous due to bandwidth constraints. Another important part in match filtering is unwanted sidelobes. These sidelobes can be detected as a main part of another signal and it can be misleading. In literature, lots of methods have been proposed to reduce sidelobes. Each method has advantages and disadvantages regarding resource usage and speed. In this work, match filtering is implemented in time and frequency domain and then sidelobe reduction techniques are examined. Due to the results the sidelobe reduction methods are added to the filter implementation. Then match filter is implemented as customizable and parametric soft IP core. This IP Core makes easy to implement the match filter in any configuration.
引用
收藏
页码:887 / 890
页数:4
相关论文
共 50 条
  • [41] An Efficient Median Filter in a Robot Sensor Soft IP-Core
    Mutauranwa, Liberty
    Nleya, Magripa
    AFRICON, 2013, 2013,
  • [42] Design and Implementation of an Efficient Hardware Coprocessor IP Core for Multi-axis Servo Control Based on Universal SoC
    Xin, Jitong
    Cha, Meiyi
    Shi, Luojia
    Jiang, Xiaoliang
    Long, Chunyu
    Lin, Qichun
    Li, Hairong
    Wang, Fangcong
    Wang, Peng
    ELECTRONICS, 2023, 12 (02)
  • [43] SP-SVPWM IP Core Design for DC-to-AC Conversion
    Ngalamou, Lucien
    2021 IEEE INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS), 2021, : 490 - 493
  • [44] A hardware implementation of nonlinear correlation filters
    Martinez-Diaz, Saul
    Castaneda-Giron, Hugo
    APPLICATIONS OF DIGITAL IMAGE PROCESSING XXXIV, 2011, 8135
  • [45] FPGA Implementation of Dynamically Tunable Filters
    Senthilkumar, E.
    Manikandan, J.
    Agrawal, V. K.
    2014 INTERNATIONAL CONFERENCE ON ADVANCES IN COMPUTING, COMMUNICATIONS AND INFORMATICS (ICACCI), 2014, : 1852 - 1857
  • [46] An Optimized GPU Implementation of the MVDR Beamformer for Active Sonar Imaging
    Buskenes, Jo Inge
    Asen, Jon Petter
    Nilsen, Carl-Inge Colombo
    Austeng, Andreas
    IEEE JOURNAL OF OCEANIC ENGINEERING, 2015, 40 (02) : 441 - 451
  • [47] FPGA implementation of FIR Nyquist filters
    Abdulhamid, H.
    Lee, R.
    Abdel-Raheem, E.
    INFORMATION PROCESSING IN THE SERVICE OF MANKIND AND HEALTH, 2006, : 123 - +
  • [48] FPGA Implementation of Reconfigurable Adaptive Filters
    Shiva, Ajay
    Senthilkumar, E.
    Manikandan, J.
    Agrawal, V. K.
    2017 2ND IEEE INTERNATIONAL CONFERENCE ON WIRELESS COMMUNICATIONS, SIGNAL PROCESSING AND NETWORKING (WISPNET), 2017, : 2544 - 2547
  • [49] Design of I2S bus IP core based on FPGA
    Li, LY
    Feng, ZH
    ICEMI 2005: Conference Proceedings of the Seventh International Conference on Electronic Measurement & Instruments, Vol 1, 2005, : 704 - 707
  • [50] Reconfigurable CRC IP core design on Xilinx Spartan 3AN FPGA
    El-Medany W.M.
    International Journal of Computer Applications in Technology, 2017, 55 (04) : 257 - 265