IMPLEMENTATION OF MATCH FILTERS AS IP CORE FOR SONAR APPLICATIONS

被引:0
|
作者
Karabalkan, Melike Atay [1 ]
Oner, Mehmet [1 ]
机构
[1] ODTU TEKNOKENT, Koc Bilgi & Savunma Teknol, Ankara, Turkey
来源
2015 23RD SIGNAL PROCESSING AND COMMUNICATIONS APPLICATIONS CONFERENCE (SIU) | 2015年
关键词
FPGA; Match Filtering; Sonar; IP Core;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Matched Filtering is an important part of the radar and sonar systems. Implementation of match filtering in time or frequency domain can be more advantageous due to bandwidth constraints. Another important part in match filtering is unwanted sidelobes. These sidelobes can be detected as a main part of another signal and it can be misleading. In literature, lots of methods have been proposed to reduce sidelobes. Each method has advantages and disadvantages regarding resource usage and speed. In this work, match filtering is implemented in time and frequency domain and then sidelobe reduction techniques are examined. Due to the results the sidelobe reduction methods are added to the filter implementation. Then match filter is implemented as customizable and parametric soft IP core. This IP Core makes easy to implement the match filter in any configuration.
引用
收藏
页码:887 / 890
页数:4
相关论文
共 50 条
  • [1] Memristor FPGA IP Core Implementation for Analog and Digital Applications
    Tolba, Mohammed F.
    Fouda, Mohammed E.
    Hezayyin, Haneen G.
    Madian, Ahmed H.
    Radwan, Ahmed G.
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2019, 66 (08) : 1381 - 1385
  • [2] IMPLEMENTATION OF GAIN CONTROL AS IP CORE
    Karabalkan, Melike Atay
    Ermis, Ercan
    Oner, Mehmet
    2016 24TH SIGNAL PROCESSING AND COMMUNICATION APPLICATION CONFERENCE (SIU), 2016, : 321 - 324
  • [3] IP Core Based on the Kalman Filter Algorithm in the FPGA Implementation
    Zhao, Xue
    Liu, Quan
    Wang, Xiaofei
    MANUFACTURING PROCESS AND EQUIPMENT, PTS 1-4, 2013, 694-697 : 1093 - 1097
  • [4] Parallel design and implementation of Error Diffusion Algorithm and IP core for FPGA
    Yang, Pengfei
    Wang, Quan
    Zhang, Jiyang
    MULTIMEDIA TOOLS AND APPLICATIONS, 2016, 75 (08) : 4723 - 4733
  • [5] Design and Implementation of IP Core for RoadRunneR-128 Block Cipher
    Raj, Mitha
    Joseph, Shinta K.
    Tomy, Josemon
    Niveditha, K. S.
    Johnson, Anna
    Nandakumar, R.
    Raj, Mitu
    2017 INTERNATIONAL CONFERENCE ON PUBLIC KEY INFRASTRUCTURE AND ITS APPLICATIONS (PKIA 2017), 2017, : 57 - 62
  • [6] Parallel design and implementation of Error Diffusion Algorithm and IP core for FPGA
    Pengfei Yang
    Quan Wang
    Jiyang Zhang
    Multimedia Tools and Applications, 2016, 75 : 4723 - 4733
  • [7] AXI-based SpaceFibre IP Core Implementation SpaceFibre, Poster Paper
    Jungewelter, D.
    Cozzi, D.
    Kleibrink, D.
    Korf, S.
    Hagemeyer, J.
    Porrmann, M.
    Ilstad, J.
    PROCEEDINGS OF THE 2014 6TH INTERNATIONAL SPACEWIRE CONFERENCE (SPACEWIRE), 2014,
  • [8] The design and implementation of a reconfigurable USART IP core for embedded computing with support for networks
    El-Mousa, Ali H.
    Anssari, Nasser
    Al-Suyyagh, Ashraf
    Al-Zubi, Hamzah
    WORLD CONGRESS ON ENGINEERING 2008, VOLS I-II, 2008, : 170 - +
  • [9] FPGA-Based Implementation of Basic Image Processing Applications as Low-Cost IP Core
    Altuncu, Mehmet Ali
    Kosten, Mehmet Muzaffer
    Cavuslu, Mehmet Ali
    Sahin, Suhap
    2018 26TH SIGNAL PROCESSING AND COMMUNICATIONS APPLICATIONS CONFERENCE (SIU), 2018,
  • [10] IP core implementation of a self-organizing neural network
    Hendry, DC
    Duncan, AA
    Lightowler, N
    IEEE TRANSACTIONS ON NEURAL NETWORKS, 2003, 14 (05): : 1085 - 1096