Power Saving and Noise Reduction of 28nm CMOS RF System Integration Using Integrated Fan-Out Wafer Level Packaging (InFO-WLP) Technology

被引：0

作者：

Wang, Chuei-Tang ^{[1
]}

Hsieh, Jeng-Shien ^{[1
]}

Chang, Victor C. Y. ^{[1
]}

Yeh, En-Hsiang ^{[1
]}

Kuo, Feng-Wei ^{[1
]}

Chen, Hsu-Hsien ^{[1
]}

Chen, Chih-Hua ^{[1
]}

Chen, Ron ^{[1
]}

Lu, Ying-Ta ^{[1
]}

Jou, Chewn-Pu ^{[1
]}

Tsai, Hao-Yi ^{[1
]}

Liu, C. S. ^{[1
]}

Yu, Doug C. H. ^{[1
]}

机构：

[1] Taiwan Semicond Mfg Co Ltd, Res & Dev, Hsinchu, Taiwan

来源：

2015 INTERNATIONAL 3D SYSTEMS INTEGRATION CONFERENCE (3DIC 2015) | 2015年

关键词：

RF system; solenoidal inductor; fan-out wafer level package; Q-factor; LNA; VCO;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

An integration of 28 nm CMOS RF system with 3D solenoidal inductors (3DSI) in integrated fan-out (InFO) wafer level package technology is studied. The 3DSI provides the performance of Q-factor of 51 and isolation of -53 dB. With the 3DSI, the RF system in the InFO technology results in power saving by 58% and noise reduction by 80% in LNA and VCO, respectively, compared with those in RF SoC system. The InFO technology provides a novel solution for RF system integration.

引用

页数：4

共 17 条

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