FPGA implementation of an optimized coefficients pulse shaping FIR filters

This paper presents the design and FPGA implementation for different order pulse shaping finite impulse response (FIR) filters. In this paper, the coefficients of the implemented filters have been modified with an optimization algorithm proposed in an earlier work. The use of this algorithm results in reducing the number of non-zero coefficients used to represent the filter's frequency response. Reducing the number of non-zero coefficients optimizes the implementation process especially when dealing with high order filters and when using lookup table (LUT) based techniques such as distributed arithmetic (DA). The designs have been downloaded to Xilinx Virtex-II FPGA and encouraging results were obtained. Hence, high-speed multiplierless design with a minimized number of arithmetic operations for different order pulse shaping FIR filters is achieved.