Dual cache architecture for low cost and high performance

被引:1
|
作者
Lee, JH [1 ]
Park, GH
Kim, SD
机构
[1] Yonsei Univ, Dept Comp Sci, Seoul 120749, South Korea
[2] Samsung Elect Co, Suwon, South Korea
关键词
memory hierarchy; dual data cache; temporal locality; spatial locality; prefetching;
D O I
10.4218/etrij.03.0303.0015
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
We present a high performance cache structure with a hardware prefetching mechanism that enhances exploitation of spatial and temporal locality. Temporal locality is exploited by selectively moving small blocks into the direct-mapped cache after monitoring their activity in the spatial buffer. Spatial locality is enhanced by intelligently prefetching a neighboring block when a spatial buffer hit occurs. We show that the prefetch operation is highly accurate: over 90% of all prefetches generated are for blocks that are subsequently accessed. Our results show that the system enables the cache size to be reduced by a factor of four to eight relative to a conventional direct-mapped cache while maintaining similar performance.
引用
收藏
页码:275 / 287
页数:13
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