A low voltage design technique for low noise RF integrated Circuits

被引：0

作者：

Abou-Allam, E ^{[1
]}

Manku, T ^{[1
]}

机构：

[1] Univ Waterloo, Dept Elect & Comp Engn, Ctr Wireless Commun, RF Technol Grp, Waterloo, ON N2L 3G1, Canada

来源：

ISCAS '98 - PROCEEDINGS OF THE 1998 INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-6 | 1998年

关键词：

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

Analysis and optimization of the bias conditions and noise parameters of MOS devices are presented. A design technique based on a narrowband LC-folded cascode topology is proposed for low voltage RF integrated Circuits. The technique is applied to the design of a 1V LNA operating at 1.9 GHz using a 0.5 mu m CMOS technology. Simulation results show that the LNA provide a noise figure of 1.7 dB, gain of 10 dB, and is well matched at the input. The LNA also provides a minimum noise figure of 1.6 dB.

引用

页码：C373 / C377

页数：5

共 50 条

[21] Guest Editorial: Low Voltage Low Power Integrated Circuits and Systems
Khateb, Fabian
Kulej, Tomasz
IET CIRCUITS DEVICES & SYSTEMS, 2018, 12 (06) : 669 - 670
[22] Low-voltage low-power CMOS RF low noise amplifier
Salama, Mohammed K.
Soliman, Ahmed M.
AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS, 2009, 63 (06) : 478 - 482
[23] Low noise gain enhanced circuits for low voltage low power CMOS systems
Falconi, C
Di Natale, C
D'Amico, A
ISIE 2002: PROCEEDINGS OF THE 2002 IEEE INTERNATIONAL SYMPOSIUM ON INDUSTRIAL ELECTRONICS, VOLS 1-4, 2002, : 1346 - 1351
[24] MTCMOS Low-Power Design Technique (LPDT) for Low-Voltage Pipelined Microprocessor Circuits
Hsu, C. B.
Kuo, J. B.
2014 14TH INTERNATIONAL SYMPOSIUM ON INTEGRATED CIRCUITS (ISIC), 2014, : 328 - 331
[25] Noise Tolerance Enhancement in Low Voltage Dynamic Circuits
Mazumdar, Kaushik
Pattanaik, Manisha
DTIS: 2009 4TH IEEE INTERNATIONAL CONFERENCE ON DESIGN & TECHNOLOGY OF INTEGRATED SYSTEMS IN NANOSCALE ERA, PROCEEDINGS, 2009, : 23 - 27
[26] Noise Tolerance Enhancement in Low Voltage Dynamic Circuits
Mazumdar, Kaushik
Pattanaik, Manisha
2009 INTERNATIONAL CONFERENCE ON EMERGING TRENDS IN ELECTRONIC AND PHOTONIC DEVICES AND SYSTEMS (ELECTRO-2009), 2009, : 84 - 87
[27] Ultra-low voltage analog integrated circuits
Chatterjee, Shouri
Tsividis, Yannis
Kinget, Peter
IEICE TRANSACTIONS ON ELECTRONICS, 2006, E89C (06): : 673 - 680
[28] Very Low Voltage testing of SOI integrated circuits
MacDonald, E
Touba, NA
20TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS, 2002, : 25 - 30
[29] THE DESIGN OF INPUT CIRCUITS FOR LOW NOISE FIGURE
LEBENBAUM, MT
PROCEEDINGS OF THE INSTITUTE OF RADIO ENGINEERS, 1948, 36 (03): : 380 - 380
[30] Decoupling Capacitor Design Strategy for Minimizing Supply Noise of Ultra Low Voltage Circuits
Seok, Mingoo
2012 49TH ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC), 2012, : 968 - 973

← 1 2 3 4 5 →