A low voltage design technique for low noise RF integrated Circuits

被引：0

作者：

Abou-Allam, E ^{[1
]}

Manku, T ^{[1
]}

机构：

[1] Univ Waterloo, Dept Elect & Comp Engn, Ctr Wireless Commun, RF Technol Grp, Waterloo, ON N2L 3G1, Canada

来源：

ISCAS '98 - PROCEEDINGS OF THE 1998 INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-6 | 1998年

关键词：

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

Analysis and optimization of the bias conditions and noise parameters of MOS devices are presented. A design technique based on a narrowband LC-folded cascode topology is proposed for low voltage RF integrated Circuits. The technique is applied to the design of a 1V LNA operating at 1.9 GHz using a 0.5 mu m CMOS technology. Simulation results show that the LNA provide a noise figure of 1.7 dB, gain of 10 dB, and is well matched at the input. The LNA also provides a minimum noise figure of 1.6 dB.

引用

页码：C373 / C377

页数：5

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