Performance Evaluation of Intel® Transactional Synchronization Extensions for High-Performance Computing

被引:66
|
作者
Yoo, Richard M. [1 ]
Hughes, Christopher J. [1 ]
Lai, Konrad [2 ]
Rajwar, Ravi [2 ]
机构
[1] Intel Labs, Parallel Comp Lab, Santa Clara, CA 95054 USA
[2] Intel Architecture Grp, Intel Architecture Dev Grp, Hillsboro, OR 97124 USA
来源
2013 INTERNATIONAL CONFERENCE FOR HIGH PERFORMANCE COMPUTING, NETWORKING, STORAGE AND ANALYSIS (SC) | 2013年
关键词
Transactional Memory; High-Performance Computing;
D O I
10.1145/2503210.2503232
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Intel has recently introduced Intel (R) Transactional Synchronization Extensions (Intel (R) TSX) in the Intel 4th Generation Core (TM) Processors. With Intel TSX, a processor can dynamically determine whether threads need to serialize through lock-protected critical sections. In this paper, we evaluate the first hardware implementation of Intel TSX using a set of high-performance computing (HPC) workloads, and demonstrate that applying Intel TSX to these workloads can provide significant performance improvements. On a set of real-world HPC workloads, applying Intel TSX provides an average speedup of 1.41x. When applied to a parallel user-level TCP/IP stack, Intel TSX provides 1.31x average bandwidth improvement on network intensive applications. We also demonstrate the ease with which we were able to apply Intel TSX to the various workloads.
引用
收藏
页数:11
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