Capacitor-less, Long-Retention (>400s) DRAM Cell Paving the Way towards Low-Power and High-Density Monolithic 3D DRAM

被引：120

作者：

Belmonte, A. ^{[1
]}

Oh, H. ^{[1
]}

Rassoul, N. ^{[1
]}

Donadio, G. L. ^{[1
]}

Mitard, J. ^{[1
]}

Dekkers, H. ^{[1
]}

Delhougne, R. ^{[1
]}

Subhechha, S. ^{[1
]}

Chasin, A. ^{[1
]}

van Setten, M. J. ^{[1
]}

Kljucar, L. ^{[1
]}

Mao, M. ^{[1
]}

Puliyalil, H. ^{[1
]}

Pak, M. ^{[1
]}

Teugels, L. ^{[1
]}

Tsvetanova, D. ^{[1
]}

Banerjee, K. ^{[1
]}

Souriau, L. ^{[1
]}

Tokei, Z. ^{[1
]}

Goux, L. ^{[1
]}

Kar, G. S. ^{[1
]}

机构：

[1] IMEC, Kapeldreef 75, B-3001 Leuven, Belgium

来源：

2020 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM) | 2020年

关键词：

D O I：

10.1109/IEDM13553.2020.9371900

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We report for the first time a fully 300-mm stacking-compatible capacitor-less DRAM cell with >400s retention time by integrating two IGZO-TFTs in a 2T0C configuration. We optimize the single IGZO-TFT performances by engineering the materials surrounding the IGZO layer and the transistor layout parameters. We thus introduce a novel IGZO-TFT device and demonstrate a scaled transistor (W = 70 nm, L = 45 nm) with optimal Vth reproducibility on 300-mm wafers. By integrating the IGZO-TFTs in a 2T0C configuration, we systematically assess reproducible long retention time for different transistor dimensions, thanks to the extremely low extracted IGZO-TFT off-current (similar to 3x10(-19)A/mu m).

引用

页数：4

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Capacitor-less, Long-Retention (&gt;400s) DRAM Cell Paving the Way towards Low-Power and High-Density Monolithic 3D DRAM

Capacitor-less, Long-Retention (>400s) DRAM Cell Paving the Way towards Low-Power and High-Density Monolithic 3D DRAM